TMS320VC5507_14 Datasheet, PDF (50/137 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
15
Reserved
R, 0000 0000 0000 0
3
2
DPLLSTAT
R, 1
1
APLLSTAT
R, 0
0
PLLSEL
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−18. USB PLL Selection and Status Register Bit Layout
Table 3−16. USB PLL Selection and Status Register Bit Functions
BIT
NO.
15−3
BIT
NAME
Reserved
2 DPLLSTAT
1 APLLSTAT
0
PLLSEL
RESET
VALUE
0
1
0
0
FUNCTION
Reserved bits. Always write 0.
Status bit indicating if the DPLL is the source for the USB module clock.
DPLLSTAT = 0
DPLLSTAT = 1
The DPLL is not the USB module clock source.
The DPLL is the USB module clock source.
Status bit indicating if the APLL is the source for the USB module clock.
APLLSTAT = 0
APLLSTAT = 1
The APLL is not the USB module clock source.
The APLL is the USB module clock source.
USB module clock source selection bit.
PLLSEL = 0
PLLSEL = 1
DPLL is selected as USB module clock source.
APLL is selected as USB module clock source.
15
12
11
10
MULT
DIV
R/W, 0000
R/W, 0
COUNT
R, 0000 0000
3
2
ON
R/W, 0
1
MODE
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−19. USB APLL Clock Mode Register Bit Layout
0
STAT
R, 0
BIT
BIT
NO.
NAME
15−12 MULT
11
DIV
10−3 COUNT
Table 3−17. USB APLL Clock Mode Register Bit Functions
RESET
VALUE
FUNCTION
PLL Multiply Factor K. Multiply Factor K, combined with DIV and MODE, determines the final PLL output
0
clock frequency.
K = MULT[3:0] + 1
PLL Divide Factor (D) selection bit for PLL multiply mode operation. DIV, combined with K and MODE,
determines the final PLL output clock frequency. When the PLL is operating in multiply mode:
0
DIV = 0
PLL Divide Factor D = 1
DIV = 1
PLL Divide Factor D = 2 if K is odd
PLL Divide Factor D = 4 if K is even
8-bit counter for PLL lock timer. When the MODE bit is set to 1, the COUNT field starts decrementing by 1
0
at the rate of CLKIN/16. When COUNT decrements to 0, the STAT bit is set to 1 and the PLL enabled clock
is sourced to the USB module.
50 SPRS244J
April 2004 − Revised January 2008