TMS320VC5507_14 Datasheet, PDF (101/137 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.9 External Interrupt Timings
Table 5−16 assumes testing over recommended operating conditions (see Figure 5−18).
Table 5−16. External Interrupt Timing Requirements^†
CVDD = 1.2 V
NO.
CVDD = 1.35 V
MIN MAX
I1 tw(INTH)A
Pulse width, interrupt high, CPU active
2P
I2 tw(INTL)A
Pulse width, interrupt low, CPU active
3P
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
CVDD = 1.6 V
MIN MAX
2P
UNIT
ns
3P
ns
I1
INTn
I2
Figure 5−18. External Interrupt Timings
5.10 Wake-Up From IDLE
Table 5−17 assumes testing over recommended operating conditions (see Figure 5−19).
Table 5−17. Wake-Up From IDLE Switching Characteristics^†
NO.
PARAMETER
CVDD = 1.2 V
CVDD = 1.35 V
MIN TYP MAX
CVDD = 1.6 V
UNIT
MIN TYP MAX
Delay time, wake-up event low to clock
ID1 td(WKPEVTL-CLKGEN) generation enable
(CPU and clock domain idle)
1.25‡
1.25‡
ms
Hold time, clock generation enable to
ID2 th(CLKGEN-WKPEVTL) wake-up event low
3P§
(CPU and clock domain in idle)
3P§
ns
ID3 tw(WKPEVTL)
Pulse width, wake-up event low
(for CPU idle only)
3P
3P
ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{Estimated data based on 12-MHz crystal used with on-chip oscillator at 25°C. This number will vary based on the actual crystal characteristics}
operating condition and the PC board layout and the parasitics.
§ _{Following the clock generation domain idle, the INTx becomes level-sensitive and stays that way until the low-to-high transition of INTx following}
the CPU wake-up. Holding the INTx low longer than minimum requirement will send more than one interrupt to the CPU. The number of interrupts
sent to the CPU depends on the INTx-low time following the CPU wake-up from IDLE.
X1
RESET,
INTx
ID1
ID2
ID3
Figure 5−19. Wake-Up From IDLE Timings
April 2004 − Revised January 2008
SPRS244J 101