TMS320VC5507_14 Datasheet, PDF (62/137 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
Table 3−28. Multichannel Serial Port #2
PORT ADDRESS
(WORD)
REGISTER NAME
DESCRIPTION
0x3000
DRR2_2[15:0]
Data Receive Register 2, McBSP #2
0x3001
DRR1_2[15:0]
Data Receive Register 1, McBSP #2
0x3002
0x3003
DXR2_2[15:0]
DXR1_2[15:0]
Data Transmit Register 2, McBSP #2
Data Transmit Register 1, McBSP #2
0x3004
SPCR2_2[15:0]
Serial Port Control Register 2, McBSP #2
0x3005
SPCR1_2[15:0]
Serial Port Control Register 1, McBSP #2
0x3006
RCR2_2[15:0]
Receive Control Register 2, McBSP #2
0x3007
RCR1_2[15:0]
Receive Control Register 1, McBSP #2
0x3008
XCR2_2[15:0]
Transmit Control Register 2, McBSP #2
0x3009
XCR1_2[15:0]
Transmit Control Register 1, McBSP #2
0x300A
SRGR2_2[15:0]
Sample Rate Generator Register 2, McBSP #2
0x300B
0x300C
SRGR1_2[15:0]
MCR2_2[15:0]
Sample Rate Generator Register 1, McBSP #2
Multichannel Control Register 2, McBSP #2
0x300D
MCR1_2[15:0]
Multichannel Control Register 1, McBSP #2
0x300E
RCERA_2[15:0]
Receive Channel Enable Register Partition A, McBSP #2
0x300F
RCERB_2[15:0]
Receive Channel Enable Register Partition B, McBSP #2
0x3010
XCERA_2[15:0]
Transmit Channel Enable Register Partition A, McBSP #2
0x3011
XCERB_2[15:0]
Transmit Channel Enable Register Partition B, McBSP #2
0x3012
PCR2[15:0]
Pin Control Register, McBSP #2
0x3013
RCERC_2[15:0]
Receive Channel Enable Register Partition C, McBSP #2
0x3014
0x3015
RCERD_2[15:0]
XCERC_2[15:0]
Receive Channel Enable Register Partition D, McBSP #2
Transmit Channel Enable Register Partition C, McBSP #2
0x3016
XCERD_2[15:0]
Transmit Channel Enable Register Partition D, McBSP #2
0x3017
RCERE_2[15:0]
Receive Channel Enable Register Partition E, McBSP #2
0x3018
RCERF_2[15:0]
Receive Channel Enable Register Partition F, McBSP #2
0x3019
XCERE_2[15:0]
Transmit Channel Enable Register Partition E, McBSP #2
0x301A
XCERF_2[15:0]
Transmit Channel Enable Register Partition F, McBSP #2
0x301B
RCERG_2[15:0]
Receive Channel Enable Register Partition G, McBSP #2
0x301C
RCERH_2[15:0]
Receive Channel Enable Register Partition H, McBSP #2
0x301D
0x301E
XCERG_2[15:0]
XCERH_2[15:0]
Transmit Channel Enable Register Partition G, McBSP #2
Transmit Channel Enable Register Partition H, McBSP #2
† _{Hardware reset; x denotes a “don’t care.”}
RESET VALUE^†
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0020 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
WORD
ADDRESS
REGISTER
NAME
0x3400
IODIR[7:0]
0x3401
IODATA[7:0]
0x4400
AGPIOEN[15:0]
0x4401
AGPIODIR[15:0]
0x4402
AGPIODATA[15:0]
0x4403
EHPIGPIOEN[5:0]
† _{Hardware reset; x denotes a “don’t care.”}
Table 3−29. GPIO
PIN
DESCRIPTION
RESET VALUE^†
GPIO[7:0]
GPIO[7:0]
A[15:0]
A[15:0]
A[15:0]
GPIO[13:8]
General-purpose I/O Direction Register
General-purpose I/O Data Register
Address/GPIO Enable Register
Address/GPIO Direction Register
Address/GPIO Data Register
EHPI/GPIO Enable Register
0000 0000 0000 0000
0000 0000 xxxx xxxx
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
62 SPRS244J
April 2004 − Revised January 2008