TMS320VC5507_14 Datasheet, PDF (124/137 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
HCS
E11
HAS
HDS
E19
HR/W
E20
E13
Read
E12
E15
E14
Write
E11
E12
E16
E15
E19
E20
E13
E14
HBE[1:0]
Valid
Valid
HCNTL[1:0]
HD[15:0]
(read)
HD[15:0]
(write)
Valid (10 or 00)
E5
E4
E6
Read Data
Valid (10 or 00)
E17
E18
Write Data
HRDY
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−36. EHPI Multiplexed Register Read/Write Timings
124 SPRS244J
April 2004 − Revised January 2008