TM4C129ENCPDT Datasheet, PDF (919/2014 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129ENCPDT Microcontroller
Register 32: EPI Masked Interrupt Status (EPIMIS), offset 0x218
This register is the masked interrupt status register. On read, it gives the current state of each
interrupt source (read, write, and error) after being masked via the EPIIM register. A write has no
effect.
The values returned are the ANDing of the EPIIM and EPIRIS registers. If a bit is set in this register,
the interrupt is sent to the interrupt controller.
EPI Masked Interrupt Status (EPIMIS)
Base 0x400D.0000
Offset 0x218
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DMAWRMIS DMARDMIS WRMIS RDMIS ERRMIS
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:5
4
3
Name
reserved
DMAWRMIS
DMARDMIS
Type
RO
RO
RO
Reset
0x000
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write uDMA Masked Interrupt Status
Value Description
0 The write uDMA has not completed or the interrupt is masked.
1 The write uDMA has completed and the DMAWRIM bit in the
EPIIM register is set, triggering an interrupt to the interrupt
controller.
This bit is cleared by writing a 1 to the DMAWRIC bit in the EPIEISC
register.
Read uDMA Masked Interrupt Status
Value Description
0 The read uDMA has not completed or the interrupt is masked.
1 The read uDMA has completed and the DMAWRIM bit in the
EPIIM register is set, triggering an interrupt to the interrupt
controller.
This bit is cleared by writing a 1 to the DMARDIC bit in the EPIEISC
register.
June 18, 2014
919
Texas Instruments-Production Data