TM4C129ENCPDT Datasheet, PDF (858/2014 Pages) Texas Instruments – Tiva Microcontroller

External Peripheral Interface (EPI)
Table 11-12. EPI General-Purpose Signal Connections (continued)
EPI Signal
General-Purpose General- Purpose General- Purpose General- Purpose
Signal (D8, A20) Signal (D16, A12) Signal (D24, A4)
Signal (D32)
EPI0S21
A13
A5
D21
D21
EPI0S22
A14
A6
D22
D22
EPI0S23
EPI0S24
A15
A7
D23
D23
A16
A8
A0^b
D24
EPI0S25
A17
A9
A1
D25
EPI0S26
A18
A10
A2
D26
EPI0S27
A19
A11
A3
D27
EPI0S28
WR
WR
WR
D28
EPI0S29
RD
RD
RD
D29
EPI0S30
Frame
Frame
Frame
D30
EPI0S31
Clock
Clock
Clock
D31
a. In this mode, half-word accesses are used. AO is the LSB of the address and is equivalent to the system A1 address.
b. In this mode, word accesses are used. AO is the LSB of the address and is equivalent to the system A2 address.
11.4.4.1
Bus Operation
A basic access is 1 EPI clock for write cycles and 2 EPI clocks for read cycles. An additional EPI
clock can be inserted into a write cycle by setting the WR2CYC bit in the EPIGPCFG register.
Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0
Clock
(EPI0S31)
Frame
(EPI0S30)
RD
(EPI0S29)
WR
(EPI0S28)
Address
Data
Data
858
June 18, 2014
Texas Instruments-Production Data