TM4C129ENCPDT Datasheet, PDF (38/2014 Pages) Texas Instruments – Tiva Microcontroller

Table of Contents
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
DES Revision Number (DES_REVISION), offset 0x030 .................................................. 1033
DES System Configuration (DES_SYSCONFIG), offset 0x034 ........................................ 1034
DES System Status (DES_SYSSTATUS), offset 0x038 .................................................. 1036
DES Interrupt Status (DES_IRQSTATUS), offset 0x03C ................................................. 1037
DES Interrupt Enable (DES_IRQENABLE), offset 0x040 ................................................ 1038
DES Dirty Bits (DES_DIRTYBITS), offset 0x044 ............................................................ 1039
DES DMA Interrupt Mask (DES_DMAIM), offset 0x030 .................................................. 1040
DES DMA Raw Interrupt Status (DES_DMARIS), offset 0x034 ....................................... 1041
DES DMA Masked Interrupt Status (DES_DMAMIS), offset 0x038 .................................. 1042
DES DMA Interrupt Clear (DES_DMAIC), offset 0x03C .................................................. 1043
SHA/MD5 Accelerator ................................................................................................................ 1044
Register 1: SHA Outer Digest A (SHA_ODIGEST_A), offset 0x000 .................................................. 1062
Register 2: SHA Outer Digest B (SHA_ODIGEST_B), offset 0x004 .................................................. 1062
Register 3: SHA Outer Digest C (SHA_ODIGEST_C), offset 0x008 .................................................. 1062
Register 4: SHA Outer Digest D (SHA_ODIGEST_D), offset 0x00C ................................................. 1062
Register 5: SHA Outer Digest E (SHA_ODIGEST_E), offset 0x010 .................................................. 1062
Register 6: SHA Outer Digest F (SHA_ODIGEST_F), offset 0x014 ................................................... 1062
Register 7: SHA Outer Digest G (SHA_ODIGEST_G), offset 0x018 ................................................. 1062
Register 8: SHA Outer Digest H (SHA_ODIGEST_H), offset 0x01C ................................................. 1062
Register 9: SHA Inner Digest A (SHA_IDIGEST_A), offset 0x020 ..................................................... 1062
Register 10: SHA Inner Digest B (SHA_IDIGEST_B), offset 0x024 ..................................................... 1062
Register 11: SHA Inner Digest C (SHA_IDIGEST_C), offset 0x028 .................................................... 1062
Register 12: SHA Inner Digest D (SHA_IDIGEST_D), offset 0x02C .................................................... 1062
Register 13: SHA Inner Digest E (SHA_IDIGEST_E), offset 0x030 ..................................................... 1062
Register 14: SHA Inner Digest F (SHA_IDIGEST_F), offset 0x034 ..................................................... 1062
Register 15: SHA Inner Digest G (SHA_IDIGEST_G), offset 0x038 .................................................... 1062
Register 16: SHA Inner Digest H (SHA_IDIGEST_H), offset 0x03C .................................................... 1062
Register 17: SHA Digest Count (SHA_DIGEST_COUNT), offset 0x040 .............................................. 1063
Register 18: SHA Mode (SHA_MODE), offset 0x044 ......................................................................... 1064
Register 19: SHA Length (SHA_LENGTH), offset 0x048 ................................................................... 1066
Register 20: SHA Data 0 Input (SHA_DATA_0_IN), offset 0x080 ........................................................ 1067
Register 21: SHA Data 1 Input (SHA_DATA_1_IN), offset 0x084 ........................................................ 1067
Register 22: SHA Data 2 Input (SHA_DATA_2_IN), offset 0x088 ........................................................ 1067
Register 23: SHA Data 3 Input (SHA_DATA_3_IN), offset 0x08C ....................................................... 1067
Register 24: SHA Data 4 Input (SHA_DATA_4_IN), offset 0x090 ........................................................ 1067
Register 25: SHA Data 5 Input (SHA_DATA_5_IN), offset 0x094 ........................................................ 1067
Register 26: SHA Data 6 Input (SHA_DATA_6_IN), offset 0x098 ........................................................ 1067
Register 27: SHA Data 7 Input (SHA_DATA_7_IN), offset 0x09C ....................................................... 1067
Register 28: SHA Data 8 Input (SHA_DATA_8_IN), offset 0x0A0 ....................................................... 1067
Register 29: SHA Data 9 Input (SHA_DATA_9_IN), offset 0x0A4 ....................................................... 1067
Register 30: SHA Data 10 Input (SHA_DATA_10_IN), offset 0x0A8 .................................................... 1067
Register 31: SHA Data 11 Input (SHA_DATA_11_IN), offset 0x0AC .................................................... 1067
Register 32: SHA Data 12 Input (SHA_DATA_12_IN), offset 0x0B0 .................................................... 1067
Register 33: SHA Data 13 Input (SHA_DATA_13_IN), offset 0x0B4 .................................................... 1067
Register 34: SHA Data 14 Input (SHA_DATA_14_IN), offset 0x0B8 .................................................... 1067
Register 35: SHA Data 15 Input (SHA_DATA_15_IN), offset 0x0BC ................................................... 1067
Register 36: SHA Revision (SHA_REVISION), offset 0x100 .............................................................. 1068
Register 37: SHA System Configuration (SHA_SYSCONFIG), offset 0x110 ........................................ 1069
38
June 18, 2014
Texas Instruments-Production Data