TM4C129ENCPDT Datasheet, PDF (9/2014 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129ENCPDT Microcontroller
18.4.1 Module Initialization ................................................................................................... 1196
18.4.2 Sample Sequencer Configuration ............................................................................... 1197
18.5 Register Map ............................................................................................................ 1197
18.6 Register Descriptions ................................................................................................. 1200
19 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 1285
19.1 Block Diagram ........................................................................................................... 1286
19.2 Signal Description ..................................................................................................... 1286
19.3 Functional Description ............................................................................................... 1288
19.3.1 Transmit/Receive Logic .............................................................................................. 1288
19.3.2 Baud-Rate Generation ............................................................................................... 1289
19.3.3 Data Transmission ..................................................................................................... 1290
19.3.4 Serial IR (SIR) ........................................................................................................... 1290
19.3.5 ISO 7816 Support ...................................................................................................... 1291
19.3.6 Modem Handshake Support ....................................................................................... 1292
19.3.7 9-Bit UART Mode ...................................................................................................... 1293
19.3.8 FIFO Operation ......................................................................................................... 1293
19.3.9 Interrupts .................................................................................................................. 1294
19.3.10 Loopback Operation .................................................................................................. 1295
19.3.11 DMA Operation ......................................................................................................... 1295
19.4 Initialization and Configuration .................................................................................... 1296
19.5 Register Map ............................................................................................................ 1297
19.6 Register Descriptions ................................................................................................. 1298
20 Quad Synchronous Serial Interface (QSSI) ..................................................... 1350
20.1 Block Diagram ........................................................................................................... 1350
20.2 Signal Description ..................................................................................................... 1351
20.3 Functional Description ............................................................................................... 1352
20.3.1 Bit Rate Generation ................................................................................................... 1353
20.3.2 FIFO Operation ......................................................................................................... 1353
20.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 1354
20.3.4 SSInFSS Function ..................................................................................................... 1355
20.3.5 High Speed Clock Operation ...................................................................................... 1356
20.3.6 Interrupts .................................................................................................................. 1356
20.3.7 Frame Formats ......................................................................................................... 1357
20.3.8 DMA Operation ......................................................................................................... 1364
20.4 Initialization and Configuration .................................................................................... 1364
20.4.1 Enhanced Mode Configuration ................................................................................... 1366
20.5 Register Map ............................................................................................................ 1367
20.6 Register Descriptions ................................................................................................. 1368
21 Inter-Integrated Circuit (I²C) Interface .............................................................. 1399
21.1 Block Diagram ........................................................................................................... 1400
21.2 Signal Description ..................................................................................................... 1401
21.3 Functional Description ............................................................................................... 1402
21.3.1 I²C Bus Functional Overview ...................................................................................... 1402
21.3.2 Available Speed Modes ............................................................................................. 1408
21.3.3 Interrupts .................................................................................................................. 1410
21.3.4 Loopback Operation .................................................................................................. 1411
21.3.5 FIFO and µDMA Operation ........................................................................................ 1411
21.3.6 Command Sequence Flow Charts .............................................................................. 1413
June 18, 2014
9
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