TM4C129ENCPDT Datasheet, PDF (1687/2014 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129ENCPDT Microcontroller
Bit/Field
19:17
16
Name
RS
NIS
Type
RO
Reset
0x0
Description
Received Process State
This field indicates the Receive DMA state. This field does not generate
an interrupt.
Value Description
0x0 Stopped: Reset or stop receive command issued
0x1 Running: Fetching receive transfer descriptor
0x2 reserved
0x3 Running: Waiting for receive packet
0x4 Suspended: Receive descriptor unavailable
0x5 Running: Closing receive descriptor
0x6 Writing Timestamp
0x7 Running: Transferring the receive packet data from receive
buffer to host memory
RW1C
0x0
Normal Interrupt Summary
Normal Interrupt Summary bit value is the logical OR of the following
when the corresponding interrupt bits are enabled in EMACDMAIM
register:
■ EMACDMARIS register, bit [0]: Transmit Interrupt
■ EMACDMARIS register, bit[2]: Transmit Buffer Unavailable
■ EMACDMARIS register, bit[6]: Receive Interrupt
■ EMACDMARIS register, bit[14]: Early Receive Interrupt
Only unmasked bits (interrupts for which interrupt enable is set in the
EMACDMAIM register) affect the Normal Interrupt Summary bit.
This is a sticky bit and must be cleared (by writing 1 to this bit) each
time a corresponding bit, which causes NIS to be set, is cleared.
June 18, 2014
Texas Instruments-Production Data
1687