TM4C129ENCPDT Datasheet, PDF (44/2014 Pages) Texas Instruments – Tiva Microcontroller

Table of Contents
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ............................................................... 1526
CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ............................................................... 1526
CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ............................................................... 1526
CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ............................................................... 1526
CAN Transmission Request 1 (CANTXRQ1), offset 0x100 .............................................. 1527
CAN Transmission Request 2 (CANTXRQ2), offset 0x104 .............................................. 1527
CAN New Data 1 (CANNWDA1), offset 0x120 ............................................................... 1528
CAN New Data 2 (CANNWDA2), offset 0x124 ............................................................... 1528
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ................................... 1529
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ................................... 1529
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ..................................................... 1530
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ..................................................... 1530
Ethernet Controller .................................................................................................................... 1531
Register 1: Ethernet MAC Configuration (EMACCFG), offset 0x000 ................................................. 1595
Register 2: Ethernet MAC Frame Filter (EMACFRAMEFLTR), offset 0x004 ...................................... 1602
Register 3: Ethernet MAC Hash Table High (EMACHASHTBLH), offset 0x008 .................................. 1606
Register 4: Ethernet MAC Hash Table Low (EMACHASHTBLL), offset 0x00C ................................... 1607
Register 5: Ethernet MAC MII Address (EMACMIIADDR), offset 0x010 ............................................ 1608
Register 6: Ethernet MAC MII Data Register (EMACMIIDATA), offset 0x014 ..................................... 1610
Register 7: Ethernet MAC Flow Control (EMACFLOWCTL), offset 0x018 ......................................... 1611
Register 8: Ethernet MAC VLAN Tag (EMACVLANTG), offset 0x01C ............................................... 1613
Register 9: Ethernet MAC Status (EMACSTATUS), offset 0x024 ...................................................... 1615
Register 10: Ethernet MAC Remote Wake-Up Frame Filter (EMACRWUFF), offset 0x028 ................... 1618
Register 11: Ethernet MAC PMT Control and Status Register (EMACPMTCTLSTAT), offset 0x02C ..... 1619
Register 12: Ethernet MAC Raw Interrupt Status (EMACRIS), offset 0x038 ........................................ 1621
Register 13: Ethernet MAC Interrupt Mask (EMACIM), offset 0x03C ................................................... 1623
Register 14: Ethernet MAC Address 0 High (EMACADDR0H), offset 0x040 ........................................ 1624
Register 15: Ethernet MAC Address 0 Low Register (EMACADDR0L), offset 0x044 ............................ 1625
Register 16: Ethernet MAC Address 1 High (EMACADDR1H), offset 0x048 ........................................ 1626
Register 17: Ethernet MAC Address 1 Low (EMACADDR1L), offset 0x04C ........................................ 1628
Register 18: Ethernet MAC Address 2 High (EMACADDR2H), offset 0x050 ........................................ 1629
Register 19: Ethernet MAC Address 2 Low (EMACADDR2L), offset 0x054 ......................................... 1631
Register 20: Ethernet MAC Address 3 High (EMACADDR3H), offset 0x058 ........................................ 1632
Register 21: Ethernet MAC Address 3 Low (EMACADDR3L), offset 0x05C ........................................ 1634
Register 22: Ethernet MAC Watchdog Timeout (EMACWDOGTO), offset 0x0DC ................................ 1635
Register 23: Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100 ........................................ 1636
Register 24: Ethernet MAC MMC Receive Raw Interrupt Status (EMACMMCRXRIS), offset 0x104 ...... 1639
Register 25: Ethernet MAC MMC Transmit Raw Interrupt Status (EMACMMCTXRIS), offset 0x108 ..... 1641
Register 26: Ethernet MAC MMC Receive Interrupt Mask (EMACMMCRXIM), offset 0x10C ................ 1643
Register 27: Ethernet MAC MMC Transmit Interrupt Mask (EMACMMCTXIM), offset 0x110 ................. 1645
Register 28: Ethernet MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB), offset
0x118 .......................................................................................................................... 1647
Register 29: Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision
(EMACTXCNTSCOL), offset 0x14C .............................................................................. 1648
Register 30: Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions
(EMACTXCNTMCOL), offset 0x150 .............................................................................. 1649
Register 31: Ethernet MAC Transmit Octet Count Good (EMACTXOCTCNTG), offset 0x164 ............... 1650
44
June 18, 2014
Texas Instruments-Production Data