TL16C752D-Q1 Datasheet, PDF (9/53 Pages) Texas Instruments – Dual UART With 64-Byte FIFO

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TL16C752D-Q1
SLLSET4 – FEBRUARY 2016
7.6 Timing Requirements
T_A = 0°C to 70°C, V_CC = 1.8 V to 5 V ±10% (unless otherwise noted)
t_RESET
C_P
t_3w
t_6s
t_6h
t_7w
t_9d
t_12d
t_12h
t_13w
t_15d
t_16s
t_16h
t_17d
t_18d
Reset pulse width
CP clock period
Oscillator or clock speed
Address setup time
Address hold time
IOR strobe width
Read cycle delay
Delay from IOR to data
Data disable time
IOW strobe width
Write cycle delay
Data setup time
Data hold time
Delay from IOW to output
Delay to set interrupt from
MODEM input
See Figure 1 and Figure 2
See Figure 1 and Figure 2
See Figure 2
See Figure 2
See Figure 1
See Figure 1
See Figure 1
See Figure 1
50-pF load, see Figure 3
50-pF load, see Figure 3
t_19d Delay to reset interrupt from IOR 50-pF load
t_20d Delay from stop to set interrupt See Figure 4
t_21d Delay from IOR to reset interrupt 50-pF load, see Figure 4
t_22d Delay from stop to interrupt
See Figure 7
t_23d
Delay from initial IOW reset to
transmit start
See Figure 7
t_24d
Delay from IOW to reset
interrupt
See Figure 7
t_25d Delay from stop to set RXRDY See Figure 5 and Figure 6
t_26d Delay from IOR to reset RXRDY See Figure 5 and Figure 6
t_27d Delay from IOW to set TXRDY See Figure 8 and Figure 9
t_28d Delay from start to reset TXRDY See Figure 8 and Figure 9
1.8 V
MIN MAX
200
63
16
20
15
85
85
65
35
85
85
40
35
60
70
80
1
55
1
8 24
75
1
1
70
16
LIMITS
2.5 V
3.3 V
MIN MAX MIN MAX
200
200
42
32
24
32
15
10
10
7
70
50
70
60
50
35
25
20
70
50
70
60
30
20
25
15
40
30
55
45
55
40
1
1
45
35
1
1
8 24 8 24
45
35
1
1
1
1
60
50
16
16
5V
MIN MAX
200
20
48
5
5
40
50
25
15
40
50
15
10
20
35
30
1
25
1
8 24
25
1
1
40
16
UNIT
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
baudrate
ns
baudrate
baudrate
ns
baudrate
μs
ns
baudrate
A[2:0]
CS
IOW
D[7:0]
Valid Address
t _6s
t _6h
Valid Address
t _6s
t _6h
t _13w
t _13w
t _15d
t _16s
t _16h
Valid Data
t _16s
t _16h
Valid Data
Figure 1. General Write Timing
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