TL16C752D-Q1 Datasheet, PDF (29/53 Pages) Texas Instruments – Dual UART With 64-Byte FIFO

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TL16C752D-Q1
SLLSET4 – FEBRUARY 2016
Table 7. TL16C752D-Q1 Internal Registers^{(1) (2)}
ADDRESS REGISTER
R/W
(3)
ACCESS
CONSIDERATION
000
RHR
R
THR
W
DLL ⁽⁴⁾
RW
LCR[7] = 0
LCR[7] = 1
001
IER
RW
DLH ⁽⁴⁾
RW
LCR[7] = 0
LCR[7] = 1
BIT 7
bit 7
0
bit 7
0
bit 7
CTS#
Interrupt
enable ⁽¹⁾
0
bit 7
BIT 6
BIT 5
bit 6
bit 5
0
0
bit 6
bit 5
0
0
bit 6
bit 5
RTS# Interrupt Xoff Interrupt
enable ⁽¹⁾
enable ⁽¹⁾
0
0
bit 6
bit 5
BIT 4
bit 4
0
bit 4
0
bit 4
Sleep
mode ⁽¹⁾
0
bit 4
010
011
100
101
IIR
R
FCR
W
LCR[7] = 0
FCR(0)
0
RX trigger
level
0
FCR(0)
0
CTS# / RTS#
0
RX trigger level
0
TX trigger
level ⁽¹⁾
0
Xoff
0
TX trigger
level ⁽¹⁾
0
AFR ⁽⁵⁾
RW
LCR[7:5] = 100
DLY2
0
DLY1
0
DLY0
0
RCVEN
1
EFR ⁽⁶⁾
RW
LCR[7:0] =
10111111
Auto CTS#
0
Auto RTS#
0
Special
character
detect
0
Enable
enhanced
functions
0
LCR
RW
None
DLAB & EFR Break control
enable
bit
0
0
Sets parity
0
Parity type
select
1
MCR
RW
LCR[7:0] ≠
10111111
1x / 4x
clock ⁽¹⁾
0
TCR & TLR
enable ⁽¹⁾
0
Xon any⁽¹⁾
0
Enable
loopback
0
Xon1 ⁽⁶⁾
RW
LCR[7:0] =
10111111
bit 7
1
bit 6
1
bit 5
bit 4
1
1
LSR
R
LCR[7:0] ≠
10111111
Error in RX
FIFO
0
THR & TSR
empty
1
THR empty
1
Break
interrupt
0
Xon2 ⁽⁶⁾
RW
LCR[7:0] =
10111111
bit 7
1
bit 6
1
bit 5
bit 4
1
0
BIT 3
BIT 2
bit 3
bit 2
0
0
bit 3
bit 2
0
0
bit 3
bit 2
Modem status
interrupt
0
RX line status
interrupt
0
bit 3
Interrupt
priority bit 2
0
DMA mode
select
0
485LG
0
bit 2
Interrupt
priority bit 1
0
Resets TX
FIFO
0
485RN
0
S/W flow
control bit 3
0
S/W flow
control bit 2
0
BIT 1
BIT 0
bit 1
bit 0
0
0
bit 1
bit 0
0
0
bit 1
bit 0
THR empty
interrupt
0
RX data available
interrupt
0
bit 1
Interrupt
priority bit 0
0
Resets RX
FIFO
0
IREN
0
bit 0
Interrupt status
1
Enable FIFOs
0
CONC
0
S/W flow
control bit 1
0
S/W flow control
bit 0
0
Parity enable No. of stop bits Word length
1
1
0
IRQ enable
0
bit 3
1
FIFORdy
enable
0
bit 2
1
RTS#
0
bit 1
1
Framing error
0
Parity error
0
Overrun error
0
bit 3
bit 2
bit 1
1
1
1
Word length
1
DTR#
0
bit 0
1
Data in receiver
0
bit 0
1
(1) Bits represented by the blue shaded cells can only be modified if EFR[4] is enabled, that is, if enhanced functions are enabled.
(2) For more register access information, see Figure 26.
(3) Read = R; Write = W
(4) This register is only accessible when LCR[7] = 1
(5) This register is only accessible LCR[7:5] = 100
(6) This register is only accessible when LCR = 1011 1111 (0xBF)
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