TL16C752D-Q1 Datasheet, PDF (3/53 Pages) Texas Instruments – Dual UART With 64-Byte FIFO

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TL16C752D-Q1
SLLSET4 – FEBRUARY 2016
5 Description (continued)
The two UARTs share only the data bus interface and clock source, otherwise they operate independently.
Another name for the UART function is asynchronous communications element (ACE), and these terms are used
interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two
such devices are incorporated into the TL16C752D-Q1 device.
6 Pin Configurations and Function
PFB Package
48-Pin TQFP
Top View
D5
1
D6
2
D7
3
RXB
4
RXA
5
TXRDYB
6
TXA
7
TXB
8
OPB
9
CSA
10
CSB
11
NC
12
36 RESET
35 DTRB
34 DTRA
33 RTSA
32 OPA
31 RXRDYA
30 INTA
29 INTB
28
A0
27
A1
26
A2
25
NC
N.C. – No internal connection
Pin Functions
PIN
I/O
NAME
NO.
DESCRIPTION
A0
28
I Address bit 0 select. Internal registers address selection. Refer to Figure 26 for register address map.
A1
27
I Address bit 1 select. Internal registers address selection. Refer to Figure 26 for register address map.
A2
26
I Address bit 2 select. Internal registers address selection. Refer to Figure 26 for register address map.
CDA
CDB
40
I
Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these
16
I
pins indicates that a carrier has been detected by the modem for that channel.
CSA
CSB
10
I Chip select A and B (active low). These pins enable data transfers between the user CPU and the TL16C752D-Q1
for the channel or channels addressed. Individual UART sections (A and B) are addressed by providing a low on the
11
I _{respective CSA and CSB pin.}
CTSA
CTSB
38
I Clear to send (active low). These inputs are associated with individual UART channels A and B. A low on the CTS
pins indicates the modem or data set is ready to accept transmit data from the TL16C752D-Q1 device. Status can
23
I
be checked by reading MSR[4]. These pins only affect the transmit and receive operations when auto CTS function
is enabled through the enhanced feature register (EFR[7]), for hardware flow control operation.
D0, D1, D2
D3, D4
D5, D6, D7
44, 45, 46
47, 48
1, 2, 3
I/O _{Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the}
controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream.
I/O
DSRA
DSRB
39
I
Data set ready (active low). These inputs are associated with individual UART channels A through B. A low on
20
I
these pins indicates the modem or data set is powered on and is ready for data exchange with the UART.
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