TL16C752D-Q1 Datasheet, PDF (35/53 Pages) Texas Instruments – Dual UART With 64-Byte FIFO

www.ti.com
TL16C752D-Q1
SLLSET4 – FEBRUARY 2016
8.5.9 Interrupt Enable Register (IER)
The interrupt enable register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR
interrupt, Xoff received, or CTS/RTS change of state from low to high. The INT output signal is activated in
response to interrupt generation. Table 13 shows interrupt enable register bit settings.
Table 13. Interrupt Enable Register (IER) Bit Settings⁽¹⁾
BIT
BIT SETTINGS
0
0 = Disable the RHR interrupt
1 = Enable the RHR interrupt
1
0 = Disable the THR interrupt
1 = Enable the THR interrupt
2
0 = Disable the receiver line status interrupt
1 = Enable the receiver line status interrupt
3
0 = Disable the modem status register interrupt
1 = Enable the modem status register interrupt
4
0 = Disable sleep mode
1 = Enable sleep mode
5
0 = Disable the Xoff interrupt
1 = Enable the Xoff interrupt
6
0 = Disable the RTS interrupt
1 = Enable the RTS interrupt
7
0 = Disable the CTS interrupt
1 = Enable the CTS interrupt
(1) IER[7:4] can be modified only if EFR[4] is set, that is, EFR[4] is a write enable.
Re-enabling IER[1] causes a new interrupt, if the THR is below the threshold.
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TL16C752D-Q1
Submit Documentation Feedback
35