TL16C752D-Q1 Datasheet, PDF (4/53 Pages) Texas Instruments – Dual UART With 64-Byte FIFO

TL16C752D-Q1
SLLSET4 – FEBRUARY 2016
www.ti.com
Pin Functions (continued)
PIN
NAME
DTRA
DTRB
GND
INTA
INTB
IOR
IOW
NC
OPA
OPB
RESET
RIA
RIB
RTSA
RTSB
RXA
RXB
RXRDYA
RXRDYB
TXA
TXB
TXRDYA
TXRDYB
V_CC
XTAL1
XTAL2
NO.
34
35
17
30
29
19
15
12, 24, 25,
37
32
9
36
41
21
33
22
5
4
31
18
7
8
43
6
42
13
14
I/O
O
O
Pwr
O
O
I
I
O
O
I
I
I
O
O
I
I
O
O
O
O
O
O
PWR
I
O
DESCRIPTION
Data terminal ready (active low). These outputs are associated with individual UART channels A through B. A low
on these pins indicates that the TL16C752D-Q1 is powered on and ready. These pins can be controlled through the
modem control register. Writing a 1 to MCR[0] sets the DTR output to low, enabling the modem. The output of these
pins is high after writing a 0 to MCR[0], or after a reset. These pins can also be used in the RS-485 mode to control
an external RS-485 driver or transceiver.
Power signal and power ground
Interrupt A and B (active high). These pins provide individual channel interrupts, INTA-B. INTA-B are enabled when
MCR[3] is set to a 1, interrupts are enabled in the interrupt enable register (IER) and when an interrupt condition
exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a
modem status flag is detected. INTA-B are in the high-impedance state after reset.
Read input (active low strobe). A valid low level on IOR loads the contents of an internal register defined by address
bits A0 through A2 onto the TL16C752D-Q1 device data bus (D0 through D7) for access by an external CPU.
Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus (D0 through D7) from
the external CPU to an internal register that is defined by address bits A0 through A2.
No internal connection
User defined outputs. This function is associated with individual channels A and B. The state of these pins is
defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to active mode and OP
to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state mode and OP to a logic 1 when MCR-
3 is set to a logic 0. See bit 3, modem control register (MCR bit 3). The output of these two pins is high after reset.
Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the receiver input
are disabled during reset time. For initialization details, see TL16C752D-Q1 device external reset conditions.
RESET is an active high input.
Ring indicator (active low). These inputs are associated with individual UART channels A and B. A logic low on
these pins indicates the modem has received a ringing signal from the telephone line. A low-to-high transition on
these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the modem
status register (MSR).
Request to send (active low). These outputs are associated with individual UART channels A and B. A low on the
RTS pins indicates the transmitter has data ready and waiting to send. Writing a 1 in the modem control register
(MCR[1]) sets these pins to low, indicating data is available. After a reset, these pins are set to 1. These pins only
affect the transmit and receive operation when auto-RTS function is enabled through the enhanced feature register
(EFR[6]), for hardware flow control operation.
Receive data input. These inputs are associated with individual serial channel data to the TL16C752D-Q1 device.
During the local loopback mode, these RX input pins are disabled and TX data is internally connected to the UART
RX input internally. During normal mode, RXn should be held high when no data is being received. These inputs
also can be used in IrDA mode. For more information, see IrDA Overview.
Receive ready (active low). RXRDYA and RXRDYB go low when the trigger level has been reached or a timeout
interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO.
Transmit data. These outputs are associated with individual serial transmit channel data from the TL16C752D-Q1
device. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the
UART RX input.
Transmit ready (active low). TXRDYA and TXRDYB go low when there are a trigger level number of spares
available. They go high when the TX buffer is full.
Power supply inputs
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal can be
connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 23). Alternatively, an external
clock can be connected to XTAL1 to provide custom data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator output or
buffered clock output.
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