TL16C752D-Q1 Datasheet, PDF (41/53 Pages) Texas Instruments – Dual UART With 64-Byte FIFO

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8.5.18 IrDA Overview
Receive Shift Register
TL16C752D-Q1
SLLSET4 – FEBRUARY 2016
Transmit Shift Register
IREN
RCVEN
Int_TX
TX
Int_RX
RX
IrDA Converter
To Optoelectronic
LED
From
Optoelectronic
Pin Diode
Baud Clock
Reset
Figure 30. IrDA Mode
The IrDA defines several protocols for sending and receiving serial infrared data, including rates of 115.2 kbps,
0.576 Mbps, 1.152 Mbps, and 4 Mbps. The low rate of 115.2 kbps was specified first and the others must
maintain downward compatibility with it. At the 115.2 kbps rate, the protocol implemented in the hardware is fairly
simple. It primarily defines a serial infrared data word to be surrounded by a start bit equal to 0 and a stop bit
equal to 1. Individual bits are encoded or decoded the same whether they are start, data, or stop bits. The IrDA
engine in the TL16C752D-Q1 device only evaluates single bits and follows the 115.2-kbps protocol. The 115.2-
kbps rate is a maximum rate. When both ends of the transfer are setup to a lower but matching speed, the
protocol still works. The clock used to code or sample the data is 16 times the baud rate, or 1.843-MHz
maximum. To code a 1, no pulse is sent or received for 1-bit time period, or 16 clock cycles. To code a 0, one
pulse is sent or received within a 1-bit time period, or 16 clock cycles. The pulse must be at least 1.6-μs wide
and 3 clock cycles long at 1.843 MHz. At lower baud rates the pulse can be 1.6 μs wide or as long as 3 clock
cycles. The transmitter output, TX, is intended to drive a LED circuit to generate an infrared pulse. The LED
circuits work on positive pulses. A terminal circuit is expected to create the receiver input, RX. Most, but not all,
PIN circuits have inversion and generate negative pulses from the detected infrared light. Their output is normally
high. The TL16C752D-Q1 device can decode either negative or positive pulses on RX.
8.5.19 IrDA Encoder Function
Serial data from a UART is encoded to transmit data to the optoelectronics. While the serial data input to this
block (Int_TX) is high, the output (TX) is always low, and the counter used to form a pulse on TX is continuously
cleared. After Int_TX resets to 0, TX rises on the falling edge of the 7^th 16XCLK. On the falling edge of the 10^th
16XCLK pulse, TX falls, creating a 3-clock-wide pulse. While Int_TX stays low, a pulse is transmitted during the
seventh to tenth clocks of each 16-clock bit cycle.
Int_TX
16XCLK
16 Cycles 16 Cycles 16 Cycles 16 Cycles
16XCLK
TX
1 2 3 4 5 6 7 8 10 12 14 16
Int_TX
TX
Figure 31. IrDA-SIR Encoding Scheme – Detailed
Timing Diagram
Figure 32. Encoding Scheme – Macro View
After reset, Int_RX is high and the 4-bit counter is cleared. When a falling edge is detected on RX, Int_RX falls
on the next rising edge of 16XCLK with sufficient setup time. Int_RX stays low for 16 cycles (16XCLK) and then
returns to high as required by the IrDA specification. As long as no pulses (falling edges) are detected on RX,
Int_RX remains high.
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