TL16C752D-Q1 Datasheet, PDF (42/53 Pages) Texas Instruments – Dual UART With 64-Byte FIFO

TL16C752D-Q1
SLLSET4 – FEBRUARY 2016
Int_TX
16XCLK
TX
1 2 3 4 5 6 7 8 10 12 14 16
16XCLK
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16 Cycles 16 Cycles 16 Cycles 16 Cycles
RX
Int_RX
Figure 33. IrDA-SIR Decoding Scheme – Detailed
Timing Diagram
Figure 34. IrDA-SIR Decoding Scheme – Macro
View
It is possible for jitter or slight frequency differences to cause the next falling edge on RX to be missed for one
16XCLK cycle. In that case, a 1-clock-wide pulse appears on Int_RX between consecutive 0s. It is important for
the UART to strobe Int_RX in the middle of the bit time to avoid latching this 1-clock-wide pulse. The TL16C550C
UART already strobes incoming serial data at the proper time. Otherwise, note that data is required to be framed
by a leading 0 and a trailing 1. The falling edge of that first 0 on Int_RX synchronizes the read strobe. The strobe
occurs on the 8^th 16XCLK pulse after the Int_RX falling edge and once every 16 cycles thereafter until the stop
bit occurs.
RX
16XCLK
Int_RX
1 2 3 4 5 6 7 8 10 12 14 16 1 2 3 4 5 6 7 8 10 12 14 16
Figure 35. Timing Causing 1-Clock-Wide Pulse Between Consecutive Ones
16XCLK
16 Cycles
16 Cycles
RX
Int_RX
External Strobe
7 Cycles
16 Cycles
Figure 36. Recommended Strobing for Decoded Data
42
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