NS16C2552_17 Datasheet, PDF (9/53 Pages) Texas Instruments – Dual Independent UART

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NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
TRANSMIT HOLDING REGISTER (THR)
This register holds the byte-wide transmit data (THR). This is a write-only register.
Table 4. THR (0x0)
Bit
Bit Name
R/W Def
Description
7:0
THR Data
W
Transmit Holding Register
0xXX
Tx FIFO data.
Note: This register value does not change upon MR reset.
INTERRUPT ENABLE REGISTER (IER)
This register enables eight types of interrupts for the corresponding serial channel. Each interrupt source can
individually activate the interrupt (INTR) output signal. Setting the bits of the IER to a logic 1 unmasks the
selected interrupt(s). Similarly, the interrupt can be masked off by resetting bits 0 through 7 of the Interrupt
Enable Register (IER). If not desired to be used, masking an interrupt source prevents it from going active in the
IIR and activating the INTR output signal. While interrupt sources are masked off, all system functions including
the Line Status and MODEM Status still operate in their normal manner. Table 5 shows the contents of the IER.
Table 5. IER (0x1)
Bit
Bit Name
7 CTS Int Ena
6
RTS Int Ena
5
Xoff Int Ena
4
Sleep Mode
Ena
3 Mdm Stat Int
Ena
2 Rx Line Stat Int
Ena
1 Tx_Empty Int
Ena
0 Rx_DV Int Ena
R/W
Def
Description
R/W CTS Input Interrupt Enable
0 1 = Enable the CTS to generate interrupt at low to high transition. Requires EFR 0x2.4 = 1.
0 = Disable the CTS interrupt (default).
R/W RTS Output Interrupt Enable
0 1 = Enable the RTS to generate interrupt at low to high transition. Requires EFR 0x2.4 = 1.
0 = Disable the RTS interrupt (default).
R/W Xoff Input Interrupt Enable
0 1 = Enable the software flow control character Xoff to generate interrupt. Requires EFR 0x2.4 = 1.
0 = Disable the Xoff interrupt (default).
R/W Sleep Mode Enable
0 1 = Enable the Sleep Mode for the respective channel. Requires EFR 0x2.4 = 1.
0 = Disable Sleep Mode (default).
R/W Modem Status Interrupt Enable
0 1 = Enable the Modem Status Register interrupt.
0 = Disable the Modem Status Register interrupt (default).
R/W Receive Line Status Interrupt Enable
0 An interrupt can be generated when any of the LSR bits 0x5.4:1=1. LSR 0x5.1 generates an interrupt as
soon as an overflow frame is received. LSR 0x5.4:2 generate an interrupt when there is read error from
FIFO.
1 = Enable the receive line status interrupt.
0 = Disable the receive line status interrupt (default).
R/W Tx Holding Reg Empty Interrupt Enable
0 1 = Enable the interrupt when Tx Holding Register is empty.
0 = Disable the Tx Holding Register from generating interrupt (default).
R/W Rx Data Available Interrupt Enable
0 1 = Enable the Received Data Available and FIFO mode time-out interrupt.
0 = Disable the Received Data Available interrupt (default).
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