NS16C2552_17 Datasheet, PDF (12/53 Pages) Texas Instruments – Dual Independent UART

NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
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Table 9. FCR (0x2) (continued)
Bit
Bit Name
R/W
Def
Description
5:4 Tx FIFO
Trig Level
Sel
W Transmit FIFO Trigger Level Selection
00 The transmit FIFO trigger threshold selection is only available in NS16C2752. When enabled, a transmit
interrupt is generated and TXRDY is asserted when the number of empty spaces in the FIFO exceeds the
threshold level.
For NS16C2752 with 64-byte FIFO:
FCR[5] FCR[4] Tx FIFO Trigger Level
1
1
= 56
1
0
= 32
0
1
= 16
0
0
= 8 (Default)
Refer to TRANSMIT OPERATION and DMA OPERATION for transmit FIFO descriptions.
These two bits are reserved in NS16C2552 and have no impact when they are written to.
3
DMA
W DMA Mode Select
Mode
Select
0 This bit controls the RXRDY and TXRDY initiated DMA transfer mode.
1 = DMA Mode 1. Allows block transfers. Requires FCR 0x2.0=1 (FIFO mode).
0 = DMA Mode 0 (default). Single transfers.
2
Tx FIFO
W Transmit FIFO Reset
Reset
0 This bit is only active when FCR bit 0 = 1.
1 = Reset XMIT FIFO pointers and all bytes in the XMIT FIFO (the Tx shift register is not cleared and is
cleared by MR reset). This bit has the self-clearing capability.
0 = No impact (default).
Note: Reset pointer will cause the characters in Tx FIFO to be lost.
1
Rx FIFO
W Receive FIFO Reset
Reset
0 This bit is only active when FCR bit 0 = 1.
1 = Reset RCVR FIFO pointers and all bytes in the RCVR FIFO (the Rx shift register is not cleared and is
cleared by MR reset). This bit has the self-clearing capability.
0 = No impact (default).
Note: Reset pointer will cause the characters in Rx FIFO to be lost.
0 Tx and Rx W Transmit and Receive FIFO Enable
FIFO
Enable
0 1 = Enable transmit and receive FIFO. This bit must be set before other FCR bits are written. Otherwise, the
FCR bits can not be programmed.
0 = Disable transmit and receive FIFO (default).
LINE CONTROL REGISTER (LCR)
The system programmer specifies the format of the asynchronous data communications exchange and sets the
Divisor Latch Access bit via the Line Control Register (LCR). This is a read and write register.
Table 10. LCR (0x3)
Bit
Bit Name
R/W
Default
Def
Description
7
Divisor Latch R/W Divisor Latch Access Bit (DLAB)
Ena
0
This bit must be set (logic 1) to access the Divisor Latches of the Baud Generator and the Alternate
Function Register during a read or write operation. It must be cleared (logic 0) to access any other
register.
1 = Enable access to the Divisor Latches of the Baud Generator and the AFR.
0 = Enable access to other registers (default).
12
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