NS16C2552_17 Datasheet, PDF (23/53 Pages) Texas Instruments – Dual Independent UART

NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
RECEIVER OPERATION
Each serial channel consists of an 8-bit Receive Shift Register (RSR) and a 16 (or 64) -byte by 11-bit wide
Receive FIFO. The RSR contains a 8-bit Receive Buffer Register (RBR) that is part of the Receive FIFO. The 11-
bit wide FIFO contains an 8-bit data field and a 3-bit error flag field. The RSR uses 16X clock as timing source.
(Figure 6.)
Figure 6. Rx FIFO Mode
The RSR operation is described as follows:
1. At the falling edge of the start bit, an internal timer starts counting at 16X clock. At 8th 16X clock,
approximately the middle of the start bit, the logic level is sampled. If a logic 0 is detected the start bit is
validated.
2. The validation logic continues to detect the remaining data bits and stop bit to ensure the correct framing. If
an error is detected, it is reported in LSR[4:2].
3. The data frame is then loaded into the RBR and the Receive FIFO pointer is incremented. The error tags are
updated to reflect the status of the character data in RBR. The data ready bit (LSR[0]) is set as soon as a
character is transferred from the shift register to the Receive FIFO. It is reset when the Receive FIFO is
empty.
Receive in FIFO Mode
Interrupt Mode
In the FIFO mode, FCR[0]=1, RBR can be configured to generate an interrupt after the FIFO pointer reaches a
trigger threshold. The interrupt causes CPU host to fetch the Rx character in the FIFO in a burst mode and the
transfer number is set by the trigger level. The interrupt is cleared as soon as the number of bytes in the Rx FIFO
drops below the trigger level. The Rx FIFO continues to receive new characters, and the interrupt is re-asserted
when the character reaches the trigger threshold.
To ensure the data is delivered to the host, a receive data ready time-out interrupt IIR[3] is generated when RBR
data is not fetched by the host in 4-word length long (defined in LCR[1:0]) plus 12 bit-time. The RBR interrupt is
enabled through IER[0]. This is equivalent of 3.6 to 4.7 frame-time.
The maximum time between a received character and a time-out interrupt will be 147 ms at 300 baud with an 8-
bit receive word.
Character delay time is calculated by using the BAUDOUT signal as a clock signal. This makes the delay
proportional to the baud rate.
Time-out interrupt is cleared and the timer is reset when the CPU reads one character from the Receive FIFO.
When the time-out interrupt is inactive the time-out timer is reset after a new character is received or after the
CPU reads the Receive FIFO.
Copyright © 2006–2013, Texas Instruments Incorporated
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