NS16C2552_17 Datasheet, PDF (29/53 Pages) Texas Instruments – Dual Independent UART

NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
There is a corner case in which the receipt of an Xoff by the local UART can occur just after it has sent the last
character of a data transfer and is ready to close the transmission. If in so doing the driver disables the local
UART, it may not receive the corresponding XON and thus can remain in a flow-controlled state. This will persist
even when the UART is re-enabled for a succeeding transmission creating a lock-up situation.
To resolve this lock-up issue, the driver should implement a delay before shutting down the local transmitter at
the end of a data transfer. This delay time should be equal to the transmission time of four characters PLUS the
latency required to drain the RX FIFO on the remote side of the connection. This will allow the remote modem to
send an Xon character and for it to be received before the local transmitter shuts down.
Rx Trigge
Level
1
4
8
14
Table 29. Xon/Xoff SW Flow Control on NS16C2552
INTR Pin
Activation
1
4
8
14
Xoff Char
Sent
1
4
8
14
Xon Char
Sent
0
1
4
8
Rx Trigger
Level
8
16
56
60
Table 30. Xon/Xoff SW Flow Control on NS16C2752
INTR Pin
Activation
8
16
56
60
Xoff Char
Sent
8
16
56
60
Xon Char
Sent
0
8
16
56
SPECIAL CHARACTER DETECT
UART can detect an 8-bit special character if EFR[5]=1. When special character detect mode is enabled, the
UART compares each received character with Xoff2. If a match is found, Xoff2 is loaded into the FIFO along with
the normal received data and IIR[4] is flagged to logic 1.
The Xon and Xoff word length is programmable between 5 and 8 bits depending on LCR[1:0] with the LSB bit
mapped to bit 0. The same word length is used for special character comparison.
SLEEP MODE
To reduce power consumption, NS16C2552/2752 has a per channel sleep mode when channel is not being
used. The sleep mode requires following conditions to be met:
• Sleep mode of the respective channel is enabled (IER[4]=1).
• No pending interrupt for the respective channel (IIR[0]=1).
• Divisor is a non-zero value (DLL or DLM != 0x00).
• Modem inputs are not toggling (MSR[3:0]=0).
• Receiver input is idling at logic 1.
The channel wakes up from sleep mode and returns to normal operation when one of the following conditions is
met:
• Start bit falling edge (logic 1 to 0) is detected on receiver.
• A character is loaded into the THR or Tx FIFO
• A state change on any of the modem interface inputs, DTS, DSR, DCD, and RI.
Following the awakening, the channel can fall back into the sleep mode when all interrupt conditions are serviced
and cleared. If channel is awakened by the modem line inputs, reading the MSR resets the line inputs.
Following the awakening, the interrupts from the respective channel has to be serviced and cleared before re-
entering into the sleep mode. The NS16C2552/2752 sleep mode can be disabled by IER[4]=0.
Copyright © 2006–2013, Texas Instruments Incorporated
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