NS16C2552_17 Datasheet, PDF (25/53 Pages) Texas Instruments – Dual Independent UART

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NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Figure 9. RXRDY in DMA Mode 0
Receive Hardware Flow Control
On the line side, RTS signal provides automatic flow control to prevent data overflow in the Receive FIFO. The
RTS is used to request remote unit to suspend or resume data transmission. This feature is enabled to suit
specific application. The RTS flow control can be enabled by the following steps:
• Enable auto-RTS flow control EFR[6]=1.
• The auto-RTS function is initiated by asserting RTS output pin, MCR[1]=1.
The auto-RTS assertion and deassertion timing is based upon the Rx FIFO trigger level (Table 27 and Table 28).
Receive Flow Control Interrupt
To enable auto RTS interrupt:
• Enable auto RTS flow control EFR[6]=1.
• Enable RTS interrupt IER[6]=1.
An interrupt is generated when RTS pin makes a transition from logic 0 to 1; IIR[5] is set to logic 1.
The receive data ready interrupt (IIR[2]) generation timing is based upon the Rx FIFO trigger level (Table 27 and
Table 28).
Rx Trigger
Level
1
4
8
14
Table 27. Auto-RTS HW Flow Control on NS16C2552
INTR Pin
Activation
1
4
8
14
RTS
Desertion
2
8
14
14
RTS
Assertion
0
1
4
8
Rx Trigger
Level
8
16
56
60
Table 28. Auto-RTS HW flow Control on NS16C2752
INTR Pin
Activation
8
16
56
60
RTS
Desertion
16
56
60
60
RTS
Assertion
0
8
16
56
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