NS16C2552_17 Datasheet, PDF (30/53 Pages) Texas Instruments – Dual Independent UART

NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
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INTERNAL LOOPBACK MODE
NS16C2552 incorporates internal loopback path for design validation and diagnostic trouble shooting. In the
loopback mode, the transmitted data is looped from the transmit shift register output to the receive shift register
input internally. The system receives its transmitted data. The loopback mode is enabled by MCR[4]=1
(Figure 15).
In the loopback mode, Tx pin is held at logic 1 or mark condition while RTS and DTR are de-asserted and CTS,
DRS, CD, and RI inputs are ignored. Note that Rx input must be held at logic 1 during the loopback test. This is
to prevent false start bit detection upon exiting the loopback mode. RTS and CTS are disabled during the test.
DMA OPERATION
LSR[6:5] provide status of the transmit FIFO and LSR[0] provides the receive FIFO status. User may read the
LSR status bits to initiate and stop data transfers.
More efficient direct memory access (DMA) transfers can be setup using the RXRDY and TXRDY signals. The
DMA transfers are asserted between the CPU cycles and saves CPU processing bandwidth. In mode 0,
(FCR[3]=0), each assertion of RXRDY and TXRDY will cause a single transfer. Note that the user should verify
the interface to make sure the signaling is compatible with the DMA controller.
With built-in transmit and receive FIFO buffers it allows data to be transferred in blocks (mode 1) and it is ideal
for more efficient DMA operation that further saves the CPU processing bandwidth.
To enable the DMA mode 1, FCR[3]=1. The DMA Rx FIFO reading is controlled by RXRDY. When FIFO data is
filled to the trigger level, RXRDY asserts and the DMA burst transfer begins removing characters from Rx FIFO.
The DMA transfer stops when Rx FIFO is empty and RXRDY deasserts.
The DMA transmit operation is controlled by TXRDY and is different between the NS16C2552 and NS16C2752.
On the NS16C2552, the DMA operation is initiated when transmit FIFO becomes empty and TXRDY is asserted.
The DMA controller fills the Tx FIFO and the filling stops when FIFO is full and TXRDY is deasserted.
On the NS16C2752, the DMA transfer starts when the Tx FIFO empty space exceeds the threshold set in
FCR[5:4] and TXRDY asserts. The transfer stops when Tx FIFO is full and TXRDY desserts. The threshold
setting gives CPU more time to arbitrate and relinquish bus control to DMA controller providing higher bus
efficiency.
INFRARED MODE
NS16C2552/2752 also integrates an IrDA version 1.0 compatible infrared encoder and decoder. The infrared
mode is enabled by MCR[6]=1.
In the infrared mode, the SOUT idles at logic 0. During data transmission, the encoder transmits a 3/16 bit wide
pulse for each logic 0. With shortened transmitter-on light pulse, power saving is achieved.
On the receiving end, each light pulse detected translates to a logic 0, active low (Figure 14.)
Figure 14. IrDA Data Transmission
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