NS16C2552_17 Datasheet, PDF (22/53 Pages) Texas Instruments – Dual Independent UART

NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
Table 25. Crystal Component Requirement
Crystal Frequency Range
Crystal Type
Parameter
C1 & C2, Load Capacitance
ESR
Frequency Stability 0 to 70°C
Value
<= 24 MHz
Parallel resonant
Fundamental
10 - 22 pF
20 - 120 Ω
100 ppm
The capacitors C1 and C2 are used to adjust the load capacitance on these pins. The total load capacitance (C1,
C2 and crystal) must be within a certain range for the NS16C2552/2752 to function properly. The parallel resistor
Rp and load resistor Rs are recommended by some crystal vendors. Refer to the vendor’s crystal datasheet for
details.
Since each channel has a separate programmable clock divider, each channel can have a different baud rate.
The oscillator provides clock to the internal data transmission circuitry, writing and reading from the parallel bus
is not affected by the oscillator frequency. For circuits not using the external crystal, the clock input is XIN
(Figure 5.)
Figure 5. Clock Input Circuitry
RESET
The NS16C2552/2752 has an on-chip power-on reset that can accommodate a slow risetime power supply. The
power-on reset has a circuit that holds the device in reset state for 2²³ XIN clock cycles. For example, if the
crystal frequency is 24MHz, the reset time will be 2²³ X 1/(24 X 10⁶) = 349ms. An external active high reset can
also be applied. The default output state of the device is listed in Table 26.
SOUT1, SOUT2
OUT2
RTS1, RTS2
DTR1, DTR2
INTR1, INTR2
TXRDY1, TXRDY2
Output
Table 26. Output State After Reset
Reset State
Logic 1
Logic 1
Logic 1
Logic 1
Logic 0
Logic 0
22
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752