NS16C2552_17 Datasheet, PDF (20/53 Pages) Texas Instruments – Dual Independent UART

NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
ENHANCED FEATURE REGISTER (EFR)
This register enables the enhanced features of the device.
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Table 20. EFR (0x2, LCR = 0xBF)
Bit
Bit Name
Default
R/W
Def
Description
7 Auto CTS R/W Automatic CTS Flow Control Enable
Flow Ctl
Ena
0 1 = Enable automatic CTS flow control. Data transmission stops when CTS input deasserts to logic 1. Data
transmission resumes when CTS returns to logic 0.
0 = Automatic CTS flow control is disabled (Default)
6 Auto RTS R/W Automatic RTS Flow Control Enable
Flow Ctl
Ena
0 By setting EFR[6] to logic 1, RTS output can be used for hardware flow control. When Auto RTS is selected,
an interrupt is generated when the receive FIFO is filled to the programmed trigger level and RTS de-asserts
to a logic 1. The RTS output must be logic 0 before the auto RTS can take effect. RTS pin functions as a
general purpose output when hardware flow control is disabled.
1 = Enable automatic RTS flow control.
0 = Automatic RTS flow control is disabled (Default)
5
Special
R/W Special Character Detect Enable
Char Det
Ena
0 1 = Special character detect enabled. The UART compares each incoming received character with data in
Xoff-2 register (0x4, LCR = 0xBF). If a match is found, the received data will be transferred to FIFO and
IIR[4] is set to indicate the detection of a special character if IER[5] = 1. Bit 0 corresponds with the LSB of
the received character. If flow control is set for comparing Xon1, Xoff1 (EFR[1:0] = 10) then flow control and
special character work normally; If flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow
control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special
character interrupt if IER[5] is enabled. Special character interrupts are cleared automatically after the next
received character.
0 = Special character detect disabled. (Default)
4 Enhanced R/W Enhanced Function Bits Enable
Fun Bit Ena
0
This bit enables IER[7:4], FCR[5:4], and MCR [7:5] to be changed. After changing the enhanced bits, EFR[4]
can be cleared to logic 0 to latch in the updated values. EFR[4] allows compatibility with the legacy mode
software by disabling alteration of the enhanced functions.
1 = Enables writing to IER[7:4], FCR[5:4], and MCR [7:5].
0 = Disable writing to IER[7:4], FCR[5:4], MCR [7:5] and, latching in updated value. Upon reset, IER[7:4],
IIR[5:4], FCR[5:4], and MCR [7:5] are cleared to logic 0. (Default)
3:0 Software
Flow
Control Sel
R/W Software Flow Control Select
0 Single character and dual sequential character software flow control is supported. Combinations of software
flow control can be selected by programming the bits.
EFR[3] EFR[2]
1
1
1
0
0
1
0
0
X
X
X
X
X
X
0
0
EFR[1]
1
1
1
1
1
0
0
0
EFR[0]
1
1
1
1
0
1
0
0
Rx Flow Control
Rx compares Xon1 & Xon2, Xoff1 & Xoff2
Rx compares Xon1 or Xon2, Xoff1 or Xoff2
Rx compares Xon1 or Xon2, Xoff1 or Xoff2
Rx compares Xon1 & Xon2, Xoff1 & Xoff2
Rx compares Xon1, Xoff1
Rx compares Xon2, Xoff2
No Rx flow control
No Tx & Rx flow control (default)
EFR[3]
1
1
0
0
EFR[2]
1
0
1
0
EFR[1]
X
X
X
X
EFR[0]
X
X
X
X
Tx Flow Control
Tx Xon1 and Xon2, Xoff1 and Xoff2
Tx Xon1, Xoff1
Tx Xon2, Xoff2
No Tx flow control
20
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