NS16C2552_17 Datasheet, PDF (16/53 Pages) Texas Instruments – Dual Independent UART

NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
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Table 12. LSR (0x5) (continued)
Bit
Bit Name
R/W
Def
Description
5
THR Empty
R THR Empty
1
This bit is the Transmitter Holding Register Empty (THRE) flag. In the 16450 mode bit 5 indicates
that the associated serial channel is ready to accept a new character for transmission. In addition,
this bit causes the DUART to issue an interrupt to the CPU when the Transmit Holding Register
Empty interrupt enable is set.
1 = In 16450 mode, whenever a character is transferred from the Transmitter Holding Register into
the Transmitter Shift Register, or in FIFO mode when the Tx FIFO is empty (default).
0 = In 16450 mode, this bit is reset to logic 0 concurrently with the loading of the Transmitter Holding
Register by the CPU. In FIFO mode, it is cleared when at least 1 byte is written to the Tx FIFO.
4
Rx Break
Interrupt
R Receive Break Interrupt Indicator
0
This bit is the Break Interrupt (BI) indicator.
1 = Whenever the received data input is held in the Spacing (logic 0) state for longer than a full
frame transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).
0 = No break condition (default).
This bit is reset to 0 whenever the CPU reads the contents of the Line Status Register or when the
next valid character is loaded into the Receiver Buffer Register.
In the FIFO Mode this condition is associated with the particular character in the FIFO it applies to. It
is revealed to the CPU when its associated character is at the top of the FIFO. When break occurs
only one zero character is loaded into the FIFO. The next character transfer is enabled after SIN
goes to the Marking (logic 1) state and receives the next valid start bit.
3 Rx Frame Error
R Framing Error Indicator
0
This bit is the Framing Error (FE) indicator.
1= Received character did not have a valid Stop bit when the serial channel detects a logic 0 during
the first Stop bit time.
0 = No frame error (default).
The bit is reset to 0 whenever the CPU reads the contents of the Line Status Register or when the
next valid character is loaded into the Receiver Buffer Register. In the FIFO Mode this error is
associated with the particular character in the FIFO it applies to. This error is revealed to the CPU
when its associated character is at the top of the FIFO. The serial channel will try to resynchronize
after a framing error. This assumes that the framing error was due to the next start bit, so it samples
this start bit twice and then takes in the data.
2
Rx Parity Error
R Parity Error Indicator
0
This bit is the Parity Error (PE) indicator.
1 = Received data word does not have the correct even or odd parity, as selected by the even-
parity-select bit during the character Stop bit time when the character has a parity error.
0 = No parity error (default).
This bit is reset to a logic 0 whenever the CPU reads the contents of the Line Status Register or
when the next valid character is loaded into the Receiver Buffer Register. In the FIFO mode this
error is associated with the particular character in the FIFO it applies to. This error is revealed to the
host when its associated character is at the top of the FIFO.
1
Rx Overrun
Error
R Overrun Error Indicator
0
This bit is the Overrun Error (OE) indicator.
This bit indicates that the next character received was transferred into the Receiver Buffer Register
before the CPU could read the previously received character. This transfer overwrites the previous
character. It is reset whenever the CPU reads the contents of the Line Status Register. If the FIFO
mode data continues to fill the FIFO beyond the trigger level, an overrun error will occur only after
the FIFO is full and the next character has been completely received in the shift register. OE is
indicated to the CPU as soon as it happens. The character in the shift register can be overwritten,
but it is not transferred to the FIFO.
1 = Set to a logic 1 during the character stop bit time when the overrun condition exists.
0 = No overrun error (default).
0 Rx Data Ready
R Receiver Data Indicator
0
This bit is the receiver Data Ready (DR) indicator.
1 = Whenever a complete incoming character has been received and transferred into the Receiver
Buffer Register (RBR) or the FIFO. Bit 0 is reset by reading all of the data in the RBR or the FIFO.
0 = No receive data available (default).
16
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