NS16C2552_17 Datasheet, PDF (26/53 Pages) Texas Instruments – Dual Independent UART

NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
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TRANSMIT OPERATION
Each serial channel consists of an 8-bit Transmit Shift Register (TSR) and a 16-byte (or 64-byte) Transmit FIFO.
The Transmit FIFO includes a 8-bit Transmit Holding Register (THR). The TSR shifts data out at the 16X internal
clock. A bit time is 16 clock periods. The transmitter begins with a start-bit followed by data bits, asserts parity-bit
if enabled, and adds the stop-bit(s). The FIFO and TSR status is reported in the LSR[6:5].
The THR is an 8-bit register providing a data interface to the host processor. The host writes transmit data to the
THR. The THR is the Transmit FIFO input register in FIFO operation. The FIFO operation can be enabled by
FCR[0]=1. During the FIFO operation, the FIFO pointer is incremented pointing to the next FIFO location when a
data word is written into the THR.
Transmit in FIFO Mode
Interrupt mode
In the NS16C2752 FIFO mode (FCR[0]=1), when the Tx FIFO empty spaces exceed the threshold level the THR
empty flag is set (LSR[5]=1). The THR empty flag generates a TXRDY interrupt (IIR[1]=1) when the transmit
empty interrupt is enabled (IER[1]=1). Writing to THR or reading from IIR deasserts the interrupt.
There is a two-character hysteresis in interrupt generation. The host needs to service the interrupt by writing at
least two characters into the Tx FIFO before the next interrupt can be generated.
The NS16C2552 does not have the FIFO threshold level control. The interrrupt is generated when the FIFO is
completely empty.
Figure 10. Tx FIFO Mode
DMA mode
To fully take advantage of the FIFO buffer, the UART is best operating in DMA mode 1 (FCR[3]=1) when
characters are transferred in bursts. The NS16C2752 has a Tx FIFO threshold level control in register FCR[5:4].
The threshold level sets the number of empty spaces in the FIFO and determines when the TXRDY is asserted.
If the number of empty spaces in the FIFO exceeds the threshold, the TXRDY asserts initiating DMA transfers to
fill the Tx FIFO. When the empty spaces in the Tx FIFO becomes zero (i.e., FIFO is full), the TXRDY deasserts
and the DMA transfer stops. TXRDY reasserts when empty space exceeds the set threshold, starting a new
DMA transfer cycle. (Figure 11.)
The NS16C2552 does not have the FIFO threshold level control. The TXRDY is asserted when FIFO is empty
and deasserted when FIFO is full. It is equivalent of having trigger threshold set at 16 empty spaces.
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