LP3907 Datasheet, PDF (9/58 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

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LP3907
SNVS511S – JUNE 2007 – REVISED APRIL 2016
Buck Converters SW1, SW2 (continued)
Unless otherwise noted, V_IN = 3.6 V, C_IN = 10 µF, C_OUT = 10 µF, L_OUT = 2.2-µH ceramic, and T_J = 25°C.^{(1)(2)(3)(4)(5)(6)}
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
I_PEAK
I_Q ⁽⁸⁾
R_DSON (P)
R_DSON (N)
T_ON
C_IN
C_OUT
Buck1 peak switching current limit
Buck2 peak switching current limit
Quiescent current “on”
Pin-pin resistance PFET
Pin-pin resistance NFET
Turnon time
Input capacitor
Output capacitor
No load PFM mode
Start up from shutdown
Capacitance for stability
Capacitance for stability
1.5
A
1
33
µA
200
mΩ
180
mΩ
500
µs
10
µF
10
µF
(8) The I_Q can be defined as the standing current of the LP3907 when the I²C bus is active and all other power blocks have been disabled
via the I²C bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition. These two
values can be used by the system designer when the device is powered using a battery.
7.8 I/O Electrical Characteristics
Unless otherwise noted: Limits apply over the entire junction temperature range for operation, T_J = −40°C to +125°C.⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
V_IL
Input low level
V_IH
Input high level
0.4
V
1.2
(1) This specification is ensured by design.
7.9 Power-On Reset (POR) Threshold/Function
PARAMETER
TEST CONDITIONS
nPOR
nPOR = Power on reset forBuck1 and Default
Buck2
nPOR
threshold
VOL
Percentage of target voltage Buck1
or Buck2
Output level low
V_BUCK1 AND V_BUCK2 rising
V_BUCK1 OR V_BUCK2 falling
Load = IoL = 500 mA
MIN
TYP MAX UNIT
50
ms
94%
85%
0.23
0.5 V
7.10 I²C Interface Timing Requirements
Unless otherwise noted, V_IN = 3.6 V and T_J = 25°C.⁽¹⁾
ƒ_CLK
t_BF
t_HOLD
t_CLKLP
t_CLKHP
t_SU
t_DATAHLD
t_DATASU
T_SU
T_TRANS
Clock frequency
Bus-free time between start and stop
Hold time repeated start condition
CLK low period
CLK high period
Set-up time repeated start condition
Data hold time
Data set-up time
Set-up time for start condition
Maximum pulse width of spikes that
must be suppressed by the input filter
of both DATA & CLK signals
(1) This specification is ensured by design.
See ⁽¹⁾
MIN NOM MAX UNIT
400 kHz
1.3
µs
0.6
µs
1.3
µs
0.6
µs
0.6
µs
0
µs
100
ns
0.6
µs
50
ns
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