LP3907 Datasheet, PDF (21/58 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

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LP3907
SNVS511S – JUNE 2007 – REVISED APRIL 2016
Feature Description (continued)
8.3.2.9 Soft Start
The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus
reducing start-up stresses and surges. The two LP3907 buck converters have a soft-start circuit that limits in-
rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated
only if EN goes from logic low to logic high after V_IN reaches 2.8V. Soft start is implemented by increasing switch
current limit in steps of 180 mA, 300 mA, and 720 mA for Buck1; 161 mA, 300 mA, and 536 mA for Buck2
(typical switch current limit). The start-up time thereby depends on the output capacitor and load current
demanded at start-up.
8.3.2.10 Low Dropout Operation
The LP3907 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support
of the output voltage. In this way the output voltage is controlled down to the lowest possible input voltage. When
the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input
voltage needed to support the output voltage is:
V_{IN, MIN} = I_LOAD × (R_{DSON, PFET} + R_INDUCTOR) + V_OUT
where
• I_LOAD = Load current
• R_{DSON, PFET} = Drain to source resistance of PFET switch in the triode region
• R_INDUCTOR = Inductor resistance
(5)
8.3.2.11 Flexible Power Sequencing of Multiple Power Supplies
The LP3907 provides several options for power on sequencing. The two bucks can be individually controlled with
ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2.
If the user desires a set power on sequence, the chip is programmable through I²C and raise EN_T from LOW to
HIGH to activate the power on sequencing.
8.3.2.12 Power-Up Sequencing Using the EN_T Function
EN_T assertion causes the LP3907 to emerge from Standby mode to Full Operation mode at a preset timing
sequence. By default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are
500 KΩ internally pulled down, which causes the part to stay OFF until enabled. If the user wishes to use the
preset timing sequence to power on the regulators, transition the EN_T pin from Low to High. Otherwise, simply
tie the enables of each specific regulator HIGH to turn on automatically.
EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched, and the
default is set at 1 ms. As shown in Figure 32 and Figure 33, a rising EN_T edge starts a power-on sequence,
while a falling EN_T edge starts a shutdown sequence. If EN_T is high, toggling the external enables of the
regulators has no effect on the chip.
The regulators can also be programmed through I²C to turn on and off. By default, I²C enables for the regulators
turned ON.
The regulators are on following the pattern below:
Regulators on = (I²C enable) AND (External pin enable OR EN_T high).
NOTE
The EN_T power-up sequencing may also be employed immediately after V_IN is applied to
the device. However, V_IN must be stable for approximately 8 ms minimum before EN_T be
asserted high to ensure internal bias, reference, and the Flexible POR timing are
stabilized. This initial EN_T delay is necessary only upon first time device power on for
power sequencing function to operate properly. If the device is powered, the EN_T logic
must be stable for 12 ms minimum before switching state.
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