LP3907 Datasheet, PDF (30/58 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

LP3907
SNVS511S – JUNE 2007 – REVISED APRIL 2016
8.6 Register Maps
8.6.1 LP3907 Control Registers
REGISTER
ADDRESS
0x02
0x07
0x10
0x11
0x20
0x23
0x24
0x25
0x29
0x2A
0x2B
0x38
0x39
0x3A
REGISTER
NAME
ICRA
SCR1
BKLDOEN
BKLDOSR
VCCR
B1TV1
B1TV2
B1RC
B2TV1
B2TV2
B2RC
BFCR
LDO1VCR
LDO2VCR
READ/WRITE
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
REGISTER DESCRIPTION
Interrupt Status Register A
System Control 1 Register
Buck and LDO Output Voltage Enable Register
Buck and LDO Output Voltage Status Register
Voltage Change Control Register 1
Buck1 Target Voltage 1 Register
Buck1 Target Voltage 2 Register
Buck1 Ramp Control
Buck2 Target Voltage 1 Register
Buck2 Target Voltage 2 Register
Buck2 Ramp Control
Buck Function Register
LDO1 Voltage Control Registers
LDO2 Voltage Control Registers
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8.6.1.1 Interrupt Status Register (ISRA) 0x02
This register informs the System Engineer of the temperature status of the chip.
D7-D2
D1
Name
—
Temp 125°C
Access
—
R
Data
Reserved
Status bit for thermal warning
PMIC T>125°C
0 – PMIC Temp. < 125°C
1 – PMIC Temp. > 125°C
Reset
0
0
D0
—
—
Reserved
0
8.6.1.2 Control 1 Register (SCR1) 0x07
This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM
and PWM mode for the bucks, and also to select between an internal and external clock for the bucks.
Name
Access
Data
D7
—
—
Reserved
Reset 0
D6-D4
EN_DLY
R/W
Selects the preset
delay sequence from
EN_T assertion
(shown below)
D3
—
—
Reserved
Factory-Programmed 1
Default
D2
D1
FPWM2
FPWM1
R/W
R/W
Buck2 PWM /PFM Mode Buck 1 PWM /PFM
select
Mode select
0 – Auto Switch PFM - 0 – Auto Switch PFM -
PWM operation
PWM operation
1 – PWM Mode Only 1 – PWM Mode Only
Factory-Programmed
Default
Factory-Programmed
Default
D0
ECEN
R/W
Reserved
0
30
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