LP3907 Datasheet, PDF (25/58 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

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LP3907
SNVS511S – JUNE 2007 – REVISED APRIL 2016
t0 t1
t2
t3
t4
EN1
RDY1
nPOR
Case 1:
EN2
RDY2
Mask Time
nPOR
Case 2:
EN2
RDY2 _0V
Mask Time
nPOR
Counter
delay
Counter
delay
Counter
delay
Mask
Window
Mask
Window
Figure 37. nPOR Mask Window
If the EN1 and RDY1 are initiated in normal operation, then nPOR is asserted and deasserted as explained in
Figure 37.
Case 1 shows the case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent the
nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising edge. nPOR
is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards depends on the status of
both RDY1 and RDY2 lines.
Case 2 shows the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2 never
goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and RDY1,
and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW after the
masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW.
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