LP3907 Datasheet, PDF (26/58 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

LP3907
SNVS511S – JUNE 2007 – REVISED APRIL 2016
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EN1
RDY1
EN2
RDY2
POR
Delay Mask Counter
SQ
RQ
Delay
Delay Mask Counter
nPOR
Figure 38. Design Implementation of the Flexible Power-On Reset
An internal power-on reset of the device is used with EN1, and EN2 to produce a reset signal (LOW) to the delay
timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer. S
= R = 1 never occurs. The mask timers are triggered off EN1 and EN2 which are gated with RDY1, and RDY2 to
generate outputs to the final AND gate to generate the nPOR.
8.3.4 Undervoltage Lockout
The LP3907 features an undervoltage lockout circuit. The function of this circuit is to continuously monitor the
raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply
voltage is less than 2.8 VDC.
The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8 VDC
trip point for a V_IN OK – Not OK detector. This V_IN OK signal is then used to gate the enable signals to the four
regulators of the device. When VINLDO12 is greater than 2.8 VDC the four enables control the four regulators,
when VINLDO12 is less than 2.8 VDC the four regulators are disabled by the V_IN detector being in the “Not OK”
state. The circuit has built-in hysteresis to prevent chattering occurring.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The
NFET switch is on in shutdown to discharge the output. When the converter is enabled, soft start is activated. It
is recommended to disable the converter during the system power up and undervoltage conditions when the
supply is less than 2.8 V.
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