LP3907 Datasheet, PDF (28/58 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

LP3907
SNVS511S – JUNE 2007 – REVISED APRIL 2016
Programming (continued)
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NOTE
According to industry I²C standards for 7-bit addresses, the MSB of an 8-bit address is
removed, and communication actually starts with the 7th most significant bit. For the
eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte
selects the register to which the data is written. The third byte contains data to write to the
selected register.
The LP3907 has factory-programmed I²C addresses. The WQFN chip has a chip address of 60'h, while the
DSBGA chip has a chip address of 61'h.
MSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
bit7 bit6 bit5 bit4 bit3 bit2 bit1
LSB
R/W
bit0
1
1
0
0
0
0
0
I²C SLAVE address (chip address)
Figure 41. I²C Chip Address (see note above)
ack from slave
ack from slave
ack from slave
start msb Chip Address lsb w ack msb Register Add lsb ack msb DATA lsb ack stop
SCL
SDA
1 2 3 4 5 6 7 8 9 1 2 3 ...
start
id = K¶60
w ack
addr = K¶02
ack
DGGUHVV K¶$$ GDWD
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = LP3907 WQFN chip address: 0x60; DSBGA chip address: 0x61
Figure 42. I²C Write Cycle
ack stop
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the Read Cycle waveform.
ack from slave
ack from slave repeated start
ack from slave data from slave ack from master
start msb Chip Address lsb w ack msb Register Add lsb ack rs msb Chip Address lsb r ack msb DATA lsb ack stop
SCL
.
SDA
start
id = K¶60
w ack register addr = K¶10 ack rs
id = K¶60
r ack
Figure 43. I²C Read Cycle
GDWD DGGU K¶6A
ack stop
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