LP3907 Datasheet, PDF (23/58 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

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LP3907
SNVS511S – JUNE 2007 – REVISED APRIL 2016
Table 6. Power-Off Timing Specification
DESCRIPTION
t₁
Programmable delay from EN_T deassertion to V_CC_Buck1 Off
t₂
Programmable delay from EN_T deassertion to V_CC_Buck2 Off
t₃
Programmable delay from EN_T deassertion to V_CC_LDO1 Off
t₄
Programmable delay from EN_T deassertion to V_CC_LDO2 Off
MIN
NOM
MAX UNIT
1.5
ms
2
ms
3
ms
6
ms
8.3.3 Flexible Power-On Reset (Power Good with Delay)
The LP3907 is equipped with an internal power-on-reset (POR) circuit which monitors the output voltage levels
on Bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck outputs
are below 91% of the rising value, or when one or both outputs fall below 82% of the desired value. The time
delay between output voltage level and nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms) 50 ms by default.
The system designer can choose the external pullup resistor (that is, 100 kΩ) for the nPOR pin.
Case1
t1
t2
EN1
EN2
RDY1
RDY2
0V
Counter
nPOR
delay
Case2
t1
t2
EN1
EN2
RDY1
0V
RDY2
nPOR
Counter
delay
Case3
EN1
EN2
RDY1
RDY2
nPOR
t1
t2
Counter
delay
Figure 35. nPOR with Counter Delay
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