LP3907 Datasheet, PDF (37/58 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

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LP3907
SNVS511S – JUNE 2007 – REVISED APRIL 2016
8.6.1.12 Buck2 Ramp Control Register (B2RC) - 0x2B
This register allows the user to program the rate of change between the target voltages of Buck2.
Name
Access
Data
Reset
D7
----
----
Reserved
D6-D4
----
----
Reserved
0
010
Data Code
4h'0
4h'1
4h'2
4h'3
4h'4
4h'5
4h'6
4h'7
4h'8
4h'9
4h'A
4h'B - 4h'F
D3-D0
B2RS
R/W
1000
Ramp Rate mV/us
Instant
1
2
3
4
5
6
7
8
9
10
10
8.6.1.13 Buck Function Register (BFCR) – 0x38
This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less
Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the
frequency ramps up and down, centered at 2 MHz.
2 MHz
Spread Spectrum
frequency
Peak frequency deviation
2 kHz triangle
wave
10 kHz triangle
wave
Time
Figure 44. Spread Spectrum Modulation Frequency
This register also allows dynamic scaling of the nPOR Delay Timing. The LP3907 is equipped with an internal
POR circuit which monitors the output voltage levels on the buck regulators, allowing the user to more actively
monitor the power status of the chip.
The UVLO feature continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the
four voltage regulators whenever this supply voltage is less than 2.8 VDC. This prevents the user from damaging
the power source (such as battery), but can be disabled if the user wishes.
Note that if the supply to VDD_M is close to 2.8 V with a heavy load current on the regulators, the chip is in
danger of powering down due to UVLO. If the user wishes to keep the chip active under those conditions, enable
the Bypass UVLO feature.
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