LP3907 Datasheet, PDF (27/58 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

www.ti.com
LP3907
SNVS511S – JUNE 2007 – REVISED APRIL 2016
8.5 Programming
8.5.1 I²C-Compatible Serial Interface
8.5.1.1 I²C Signals
The LP3907features an I²C-compatible serial interface, using two dedicated pins: SCL and SDA for I²C clock and
data respectively. Both signals need a pullup resistor according to the I²C specification. The LP3907 interface is
an I²C slave that is clocked by the incoming SCL clock.
Signal timing specifications are according to the I²C bus specification. The maximum bit rate is 400kbit/s. See I²C
specification from NXP Semiconductors for further details.
8.5.1.2 I²C Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL); for example, the state
of the data line can only be changed when CLK is LOW.
I²C_SCL
I²C_SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 39. I²C Signals: Data Validity
8.5.1.3 I²C Start and Stop Conditions
START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as the
SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while the SCL is HIGH. The ²C master always generates START and STOP
bits. The I²C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I²C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
I²C_SDA
I²C_SCL
S
START condition
P
STOP condition
Figure 40. Start and Stop Conditions
8.5.1.4 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying acknowledgment. A receiver which has been
addressed must generate an acknowledgment (“ACK”) after each byte has been received.
After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W).
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: LP3907
Submit Documentation Feedback
27