DS64BR401_13 Datasheet, PDF (9/36 Pages) Texas Instruments – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

DS64BR401
www.ti.com
SNLS304G – JUNE 2009 – REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified. ⁽¹⁾
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DJ2
Residual Deterministic Jitter Tx Launch Amplitude = 0.8 to
at 6.4 Gbps
1.2 Vp–p, 12 meters (30 AWG),
EQx[1:0] = 1F, DEMx[1:0] = 0 dB,
VOD = 1.0 Vp-p, K28.5,
SD_TH = float, ⁽⁵⁾
0.05
0.15
UI_P-P
DJ3
Residual Deterministic Jitter Tx Launch Amplitude = 0.8 to
at 3.2 Gbps
1.2 Vp–p, 40” 4–mil FR4 trace,
EQx[1:0] = 0F, DEMx[1:0] = 0 dB,
VOD = 1.0 Vp-p, K28.5,
SD_TH = float, ⁽⁵⁾
0.05
0.12
UI_P-P
DJ4
Residual Deterministic Jitter Tx Launch Amplitude = 0.8 to
at 3.2 Gbps
1.2 Vp–p, 12 meters (30 AWG),
EQx[1:0] = 1F, DEMx[1:0] = 0 dB,
VOD = 1.0 Vp-p, K28.5,
SD_TH = float, ⁽⁵⁾
0.06
0.16
UI_P-P
RJ
Random Jitter
Tx Launch Amplitude = 0.8 to 1.2 Vp–p,
Repeating 1100b (D24.3) pattern
0.5
psrms
DE-EMPHASIS
DJ5
Residual Deterministic Jitter Tx Launch amplitude = 0.8 to
at 6.4 Gbps
1.2 Vp–p, 10” 4–mil FR4 trace,
EQx[1:0] = OFF, DEMx[1:0] = −6 dB,
VOD = 1.0 Vp-p, K28.5, RATE = 1 ⁽⁵⁾
0.09
0.20
UI_P-P
DJ6
Residual Deterministic Jitter Tx Launch amplitude = 0.8 to
at 3.2 Gbps
1.2 Vp–p, 20” 4–mil FR4 trace,
EQx[1:0] = OFF, DEMx[1:0] = −6 dB,
VOD = 1.0 Vp-p, K28.5, RATE = 0 ⁽⁷⁾
0.07
0.18
UI_P-P
(7) Typical values represent most likely parametric norms at V_DD = 2.5V, T_A = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not verified.
ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
SERIAL BUS INTERFACE DC SPECIFICATIONS
V_OL
Data (SDA) Low Level Output
I_OL = 3mA
Voltage
V_IL
Data (SDA), Clock (SCL) Input Low
Voltage
V_IH
Data (SDA), Clock (SCL) Input High
2.1
Voltage
I_PULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
4
V_DD
I_LEAK-Bus
I_LEAK-Pin
C_I
R_TERM
Nominal Bus Voltage
Input Leakage Per Bus Segment
Input Leakage Per Device Pin
Capacitance for SDA and SCL
External Termination Resistance
pull to V_DD = 2.5V ± 5% OR 3.3V ±
10%
(1)
(1) (2)
V_DD3.3,
(1) (2) (3)
V_DD2.5,
(1) (2) (3)
2.375
-200
-15
2000
1000
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 5
FSMB
Bus Operating Frequency
(4)
10
Max
0.4
0.8
3.6
3.6
+200
10
100
Units
V
V
V
mA
V
µA
µA
pF
Ω
Ω
kHz
(1) Recommended value. Parameter not tested in production.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
Copyright © 2009–2013, Texas Instruments Incorporated
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