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DS64BR401_13 Datasheet, PDF (18/36 Pages) Texas Instruments – Quad Bi-Directional Transceiver with Equalization and De-Emphasis
DS64BR401
SNLS304G – JUNE 2009 – REVISED APRIL 2013
www.ti.com
Address Register Name
0x00
Reset
0x01
PWDN Channels
0x02
PWDN Control
0x08
Pin Control Override
0x0E
CH0 - CHB0
IDLE RATE Select
0x0F
CH0 - CHB0
EQ Control
0x10
CH0 - CHB0
VOD Control
Table 9. SMBus Register Map
Bit (s) Field
7:1 Reserved
0
Reset
7:0 PWDN CHx
7:1 Reserved
0
Override PWDN
7:5 Reserved
4
Override IDLE
3
Reserved
2
Override RATE
1:0 Reserved
7:6 Reserved
5
IDLE auto
4
IDLE select
3:2 Reserved
1
RATE auto
0
RATE select
7:6 Reserved
5:0 CH0 IB0 EQ
7:6 Reserved
5:0 CH0 OB0 VOD
Type
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R/W
Default
0x00
0x00
0x00
0x00
0x00
0x0
0x20
0x00
0x03
Description
Set bits to 0.
SMBus Reset
1: Reset registers to default value
Power Down per Channel
[7]: CHA_3
[6]: CHA_2
[5]: CHA_1
[4]: CHA_0
[3]: CHB_3
[2]: CHB_2
[1]: CHB_1
[0]: CHB_0
00'h = all channels enabled
FF'h = all channels disabled
Set bits to 0.
0: Allow PWDN pin control
1: Block PWDN pin control
Set bits to 0.
0: Allow IDLE pin control
1: Block IDLE pin control
Set bit to 0.
0: Allow RATE pin control
1: Block RATE pin control
Set bits to 0.
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
Set bits to 0.
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
Set bits to 0.
IB0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ0 EQ1] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
0F = 110001 = 31'h
01 = 111000 = 38'h
1F = 110100 = 34'h
10 = 110101 = 35'h
F0 = 111010 = 3A'h
F1 = 111100 = 3C'h
Set bit to 0.
OB0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
18
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