DS64BR401_13 Datasheet, PDF (16/36 Pages) Texas Instruments – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

DS64BR401
SNLS304G – JUNE 2009 – REVISED APRIL 2013
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When SMBus is enabled, the DS64BR401 must use one of the following De-emphasis settings (Table 8).
The driver de-emphasis value is set on a per channel basis using 8 different registers. Each register (0x11, 0x18,
0x1F, 0x26, 0x2E, 0x35, 0x3C, 0x43) requires one of the following De-emphasis settings when in SMBus mode.
Table 8. De-Emphasis Register Settings (must write one of the following when in SMBus mode)
De-Emphasis Value
0.0 dB
-3.5 dB
-6 dB
-9 dB
-12 dB
Register Setting
0x01
0x38
0x88
0x90
0xA0
3 Gbps Operation
10” trace or 1 meter 28 awg cable
20” trace or 2 meters 28 awg cable
25” trace or 3 meters cable
5 meters 28 awg cable
8 meters 28 awg cable
6 Gbps Operation
5” trace or 0.5 meter 28 awg cable
10” trace or 1meters 28 awg cable
20” trace or 2 meters cable
3 meters 28 awg cable
5 meters 28 awg cable
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
RECOMMENDED SMBUS REGISTER SETTINGS
When SMBus mode is enabled (ENSMB = 1), the default register are not configured to an appropriate settings.
Below is the recommended settings to configure the EQ, VOD and DE to a medium level that supports
interconnect length of 20 inches FR4 trace or 3 to 5 meters of cable length. Please refer to ,
Table 2,Table 3,Table 4,Table 5, Table 8,Table 9 for additional information and recommended settings.
1. Reset the SMBus registers to default values:
– Write 01'h to address 0x00.
2. Set de-emphasis to -6 dB enhance for all channels (CH0–CH7):
– Write 88'h to address 0x11, 0x18, 0x1F, 0x26, 0x2E, 0x35, 0x3C, 0x43.
3. Set equalization to external pin level EQ[1:0] = 00 (~9 dB at 3 GHz) for all channels (CH0–CH7):
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