DS64BR401_13 Datasheet, PDF (22/36 Pages) Texas Instruments – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

DS64BR401
SNLS304G – JUNE 2009 – REVISED APRIL 2013
www.ti.com
Address
0x26
Register Name
CH3 - CHB3
DE Control
0x27
CH3 - CHB3
IDLE Threshold
0x2B
CH4 - CHA0
IDLE RATE Select
0x2C
CH4 - CHA0
EQ Control
0x2D
CH4 - CHA0
VOD Control
Table 9. SMBus Register Map (continued)
Bit (s) Field
7:0 CH3 OB3 DEM
7:4 Reserved
3:0 IDLE threshold
7:6 Reserved
5
IDLE auto
4
IDLE select
3:2 Reserved
1
RATE auto
0
RATE select
7:6 Reserved
5:0 CH4 IA0 EQ
7:6 Reserved
5:0 CH4 OA0 VOD
Type
R/W
R/W
R/W
R/W
R
R/W
Default
0x03
0x00
0x00
0x20
0x00
0x03
Description
OB3 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 00111000 = 38'h = −3.5 dB
0F = 10001000 = 88'h = −6.0 dB
01 = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
Set bits to 0.
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
Set bits to 0.
IA0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ0 EQ1] = Register [EN] [GST] [BST] =
Hex Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
0F = 110001 = 31'h
01 = 111000 = 38'h
1F = 110100 = 34'h
10 = 110101 = 35'h
F0 = 111010 = 3A'h
F1 = 111100 = 3C'h
Set bit to 0.
OA0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = 1400 mV
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