DS64BR401_13 Datasheet, PDF (10/36 Pages) Texas Instruments – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

DS64BR401
SNLS304G – JUNE 2009 – REVISED APRIL 2013
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ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TBUF
Bus Free Time Between Stop and
Start Condition
4.7
µs
THD:STA
Hold time after (Repeated) Start
At I_PULLUP, Max
Condition. After this period, the first
4.0
µs
clock is generated.
TSU:STA
Repeated Start Condition Setup
Time
4.7
µs
TSU:STO
Stop Condition Setup Time
4.0
µs
THD:DAT
Data Hold Time
300
ns
TSU:DAT
T_TIMEOUT
T_LOW
T_HIGH
T_LOW:SEXT
t_F
t_R
t_POR
Data Setup Time
Detect Clock Low Timeout
(4)
Clock Low Period
Clock High Period
(4)
Cumulative Clock Low Extend Time ⁽⁴⁾
(Slave Device)
Clock/Data Fall Time
(4)
Clock/Data Rise Time
(4)
Time in which a device must be
(4)
operational after power-on reset
250
ns
25
35
ms
4.7
µs
4.0
50
µs
2
ms
300
ns
1000
ns
500
ms
10
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