DS64BR401_13 Datasheet, PDF (4/36 Pages) Texas Instruments – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

DS64BR401
SNLS304G – JUNE 2009 – REVISED APRIL 2013
Pin Name
Pin Number
Differential High Speed I/O's
IA_0+, IA_0- ,
IA_1+, IA_1-,
IA_2+, IA_2-,
IA_3+, IA_3-
10, 11
12, 13
15, 16
17, 18
OA_0+, OA_0-,
OA_1+, OA_1-,
OA_2+, OA_2-,
OA_3+, OA_3-
35, 34
33, 32
31, 30
29, 28
IB_0+, IB_0- ,
IB_1+, IB_1-,
IB_2+, IB_2-,
IB_3+, IB_3-
45, 44
43, 42
40, 39
38, 37
OB_0+, OB_0-,
1, 2
OB_1+, OB_1-,
3, 4
OB_2+, OB_2-,
5, 6
OB_3+, OB_3-
7, 8
Control Pins — Shared (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBUS MODE)
SCL
50
SDA
49
AD0–AD3
54, 53, 47, 46
ENSMB = 0 (NORMAL PIN MODE)
EQA0, EQA1
EQB0, EQB1
20, 19
46, 47
DEMA0, DEMA1
DEMB0, DEMB1
49, 50
53, 54
Control Pins — Both Modes (LVCMOS)
RATE
21
Table 1. PIN DESCRIPTIONS
I/O, Type
Pin Descriptions
www.ti.com
I, CML
O, LPDS
Inverting and non-inverting CML differential inputs to the equalizer. A
gated on-chip 50Ω termination resistor connects INA_n+ to VDD and
INA_n- to VDD when enabled.
Inverting and non-inverting low power differential signaling (LPDS) 50Ω
outputs with de-emphasis. Compatible with AC coupled CML inputs.
I, CML
O, LPDS
Inverting and non-inverting CML differential inputs to the equalizer. A
gated on-chip 50Ω termination resistor connects INB_n+ to VDD and
INB_n- to VDD when enabled.
Inverting and non-inverting low power differential signaling (LPDS) 50Ω
outputs with de-emphasis. Compatible with AC coupled CML inputs.
I, LVCMOS w/
internal pull-
down
System Management Bus (SMBus) enable pin.
When pulled high provide access internal digital registers that are a
means of auxiliary control for such functions as equalization, de-
emphasis, VOD, rate, and idle detection threshold.
When pulled low, access to the SMBus registers are disabled and
SMBus function pins are used to control the Equalizer and De-Emphasis.
Please refer to SYSTEM MANAGEMENT BUS (SMBUS) AND
CONFIGURATION REGISTERS section and ELECTRICAL
CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE for
detail information.
I, LVCMOS
I, LVCMOS
O, Open Drain
I, LVCMOS w/
internal pull-
down
ENSMB = 1
SMBUS clock input pin is enabled. External pull-up resistor maybe
needed. Refer to R_TERM in the SMBus specification.
ENSMB = 1
The SMBus bi-directional SDA pin is enabled. Data input or open drain
output. External pull-up resistor is required.
Refer to R_TERM in the SMBus specification.
ENSMB = 1
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs. See section — SYSTEM
MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS
for additional information.
I, Float,
LVCMOS
I, Float,
LVCMOS
EQA/B, 3–level controls the level of equalization of the A/B sides. The
EQA/B pins are active only when ENSMB is de-asserted (Low). Each of
the 4 A/B channels have the same level unless controlled by the SMBus
control registers. When ENSMB goes high the SMBus registers provide
independent control of each lane. See Table 2,Table 3,Table 4
DEMA/B, 3–level controls the level of de-emphasis of the A/B sides. The
DEMA/B pins are only active when ENSMB is de-asserted (Low). Each
of the 4 A/B channels have the same level unless controlled by the
SMBus control registers. When ENSMB goes High the SMBus registers
provide independent control of each lane. See Table 5
I, Float,
LVCMOS
RATE, 3–level controls the pulse width of de-emphasis of the output.
RATE = 0 forces 3 Gbps,
RATE = 1 forces 6 Gbps,
RATE = Float enables auto rate detection and the pulse width (pull-back)
is set appropriately after each exit from IDLE. This requires the transition
from IDLE to ACTIVE state — OOB signal. See Table 5
4
Submit Documentation Feedback
Product Folder Links: DS64BR401
Copyright © 2009–2013, Texas Instruments Incorporated