DS64BR401_13 Datasheet, PDF (5/36 Pages) Texas Instruments – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

DS64BR401
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Pin Name
TXIDLEA,TXIDLEB
VOD0, VOD1
PWDN
Analog
SD_TH
Power
VDD
GND
NC
SNLS304G – JUNE 2009 – REVISED APRIL 2013
Table 1. PIN DESCRIPTIONS (continued)
Pin Number
24, 25
22, 23
52
I/O, Type
I, Float,
LVCMOS
I, LVCMOS w/
internal pull-
down
I, LVCMOS
Pin Descriptions
TXIDLEA/B, 3–level controls the driver output.
TXIDLEA/B = 0 disables the signal detect/squelch function for all A/B
outputs.
TXIDLEA/B = 1 forces the outputs to be muted (electrical idle).
TXIDLEA/B = Float enables the signal auto detect/squelch function and
the signal detect voltage threshold level can be adjusted using the
SD_TH pin. See Table 6
VOD[1:0] adjusts the output differential amplitude voltage level.
VOD[1:0] = 00 sets output VOD = 600 mV (Default)
VOD[1:0] = 01 sets output VOD = 800 mV
VOD[1:0] = 10 sets output VOD = 1000 mV
VOD[1:0] = 11 sets output VOD = 1200 mV
PWDN = 0 enables the device (normal operation).
PWDN = 1 disables the device (low power mode).
Pin must be driven to a logic low at all times for normal operation
27
I, ANALOG
Threshold select pin for electrical idle detect threshold. Float pin for
typical default 130 mVp-p (differential), otherwise connect resistor from
SD_TH to GND to set threshold voltage. See Table 7, Figure 6
9, 14, 36, 41, 51 Power
DAP
Power
26
Power supply pins. 2.5 V +/-5%
DAP is the large metal contact at the bottom side, located at the center
of the 54 pin WQFN package. It should be connected to the GND plane
with at least 4 via to lower the ground impedance and improve the
thermal performance of the package.
No Connect — Leave pin open
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2009–2013, Texas Instruments Incorporated
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