DS64BR401_13 Datasheet, PDF (26/36 Pages) Texas Instruments – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

DS64BR401
SNLS304G – JUNE 2009 – REVISED APRIL 2013
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Address
0x43
0x44
0x47
0x4C
0x4E
Table 9. SMBus Register Map (continued)
Register Name
CH7 - CHA3
DE Control
Bit (s) Field
7:0 CH7 OA3 DEM
CH7 - CHA3
IDLE Threshold
7:4 Reserved
3:0 IDLE threshold
EN
7:6
Digital Test Point IDLE
Detect
5
4
3:2
Global VOD Adjust
1:0
Reserved
CH2, CH3 CH6, CH7
CH0, CH1 CH4, CH5
Reserved
VOD Adjust
EN
Digital Test Point
RATE Detect
Digital Test
7
CH2, CH3 CH6, CH7
6
CH0, CH1 CH4, CH5
5:0 Reserved
7:1 Reserved
0
Block AD[3:0] pins
Type Default
R/W 0x03
R/W 0x00
R/W 0x02
R/W 0x00
R/W 0x00
Description
OA3 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced =
1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level
Control] = Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 00111000 = 38'h = −3.5 dB
0F = 10001000 = 88'h = −6.0 dB
01 = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
Set bits to 0.
0: Disabled IDLE Test Point for CH2, 3, 6, 7.
1: Enable IDLE Test Point for CH2, 3, 6, 7.
0: Disabled IDLE Test Point for CH0, 1, 4, 5.
1: Enable IDLE Test Point for CH0, 1, 4, 5.
Set bits to 0.
00 = −25%
01 = −12.5%
10 = 0% (Default)
11 = +12.5%
0: Disabled RATE Test Point for CH2, 3, 6, 7.
1: Enable RATE Test Point for CH2, 3, 6, 7.
0: Disabled RATE Test Point for CH0, 1, 4, 5.
1: Enable RATE Test Point for CH0, 1, 4, 5.
Set bits to 0.
Set bits to 0.
1: Configure GPIO pin 46, 47, 53, 54 to be
outputs.
26
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