DS64BR401_13 Datasheet, PDF (27/36 Pages) Texas Instruments – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

DS64BR401
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APPLICATION INFORMATION
SNLS304G – JUNE 2009 – REVISED APRIL 2013
GENERAL RECOMMENDATIONS
The DS64BR401 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity
design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and LPDS outputs must have a controlled differential impedance of 100Ω. It is preferable to
route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias
should be avoided if possible. If vias must be used, they should be used sparingly and must be placed
symmetrically for each side of a given differential pair. Route the differential signals away from other signals and
noise sources on the printed circuit board. See AN-1187(SNOA401) for additional information on WQFN
packages.
The graphic shown below depicts a typical microstrip trace routing design of the top and bottom layers. This
should be used as a reference to achieve the optimal system performance. Impedance discontinuities at the
differential via can be minimized or eliminated by increasing the swell around each via hole. To further improve
the signal quality, a ground via placed close to the signal via for a low inductance return current path is
recommended. When the via structure is associated with stripline trace and a thick board, further optimization
such as back drilling is often used to reduce the high frequency effects of via stubs on the signal path. To
minimize cross-talk coupling, it is recommended to have >3X gap spacing between the differential pairs. For
example, if the trace width is 5 mils with 5 mils spacing – 100Ω differential impedance (closely coupled). The gap
spacing between the differential pairs should be >15 mils.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS64BR401 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the V_DD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01 μF bypass capacitor should be
connected to each V_DD pin such that the capacitor is placed as close as possible to the DS64BR401. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
Figure 8. Typical PCB Trace Routing
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