BQ25120A Datasheet, PDF (9/67 Pages) Texas Instruments – Low IQ Highly Integrated Battery Charge Management Solution for Wearables and IoT

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bq25120A
SLUSD08 – MAY 2017
Electrical Characteristics (continued)
Circuit of Figure 1, V_(UVLO) < V_IN < V_(OVP) and V_IN > V_(BAT) + V_(SLP), T_J = –40 to 85°C and T_J = 25°C for typical values (unless
otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Fast Charge Current
Range
V_(BATUVLO) < V_(BAT) < V_(BATREG)
5
300
mA
I_(CHARGE)
Fast Charge Current
using ISET
Fast Charge Current
Accuracy
K_(ISET) /
R_(ISET)
A
–5%
5%
K_(ISET)
Fast Charge Current
Factor
5 mA > I_(CHARGE) > 300 mA
190
200
210
AΩ
Termination charge
current
Termination current programmable range over I²C
0.5
37
mA
I_(CHARGE) < 300 mA, R_(ITERM) = 15 kΩ
5
I_(TERM)
Termination Current using ^I(CHARGE) ^{< 300 mA, R}(ITERM) ^{= 4.99 kΩ}
10
IPRETERM
I_(CHARGE) < 300 mA, R_(ITERM) = 1.65 kΩ
15
I_(CHARGE) < 300 mA, R_(ITERM) = 549 Ω
20
Accuracy
I_(TERM) > 4 mA
–10%
t_DGL(TERM)
TERM deglitch time
Both rising and falling, 2-mV over-drive, t_RISE, t_FALL = 100 ns
64
Pre-charge current
Pre-charge current programmable range over I²C
0.5
10%
37
% of I_SET
% of I_SET
% of I_SET
% of I_SET
ms
mA
I_{(PRE_CHARGE)}
Pre-charge Current using
I_PRETERM
Accuracy
I_(TERM)
A
–10%
10%
V_(RCH)
Recharge threshold
voltage
Below V_(BATREG)
100
120
140
mV
t_DGL(RCHG)
Recharge threshold
deglitch time
t_FALL = 100 ns typ, V_(RCH) falling
32
ms
SYS OUTPUT
R_{DS(ON_HS)}
R_{DS(ON_LS)}
R_{DS(CH_SYS)}
MOSFET on-resistance
for SYS discharge
PMID = 3.6 V, I_(SYS) = 150 mA
PMID = 3.6 V, I_(SYS) = 150 mA
V_IN = 3.6 V, I_OUT = –10 mA into V_OUT pin
675
850
mΩ
300
475
mΩ
22
40
Ω
I_(LIMF)
I_{(LIM_SS)}
SW Current limit HS
SW Current limit LS
PMOS switch current limit
during softstart
2.2V < V_(PMID) < 5.5 V
2.2V < V_(PMID) < 5.5 V
Current limit is reduced during softstart
450
600
675
mA
450
700
850
mA
80
130
200
mA
SYS Output Voltage
Range
Programmable range, 100 mV Steps
1.1
3.3
V
V_SYS
Output Voltage Accuracy
DC Output Voltage Load
Regulation in PWM mode
V_IN = 5 V, PFM mode, I_OUT = 10 mA, V_(SYS) = 1.8 V
V_OUT = 2 V, over load range
–2.5%
0
0.01
2.5%
%/mA
DC Output Voltage Line
Regulation in PWM mode
V_OUT = 2.V, I_OUT = 100 mA, over V_IN range
0.01
%/V
LS/LDO OUTPUT
V_IN(LS)
Input voltage range for
LS/LDO
Input voltage range for
LS/LDO
Load Switch Mode
LDO Mode
0.8
6.6
V
2.2
6.6
V
V_OUT
V_LDO
ΔV_OUT / Δ V_IN
DC output accuracy
Output range for LS/LDO
DC Line regulation
DC Load regulation
Load Transient
T_J = 25°C
Over V_IN, I_OUT, temperature
Programmable Range, 0.1 V steps
V_OUT(NOM) + 0.5 V < V_IN < 6.6 V, I_OUT = 5 mA
0 mA < I_OUT < 100 mA
2 uA to 100 mA, VOUT = 1. 8V
–2%
±1%
2%
–3%
±2%
3%
0.8
3.3
V
–1%
1%
–1%
1%
–120
60
mV
R_{DS(ON_LDO)}
R_{(DSCH_LSLDO)}
FET Rdson
MOSFET on-resistance
for LS/LDO discharge
V_(VINLS) = 3.6 V
1.7V < V_(VINLS) < 6.6 V, I_LOAD = –10 mA
460
600
mΩ
20
Ω
Copyright © 2017, Texas Instruments Incorporated
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