BQ25120A Datasheet, PDF (43/67 Pages) Texas Instruments – Low IQ Highly Integrated Battery Charge Management Solution for Wearables and IoT

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bq25120A
SLUSD08 – MAY 2017
9.6.8 Load Switch and LDO Control Register
Memory location 0x07h, Reset State: 0111 110x (bq25120A)
Figure 32. Load Switch and LDO Control Register
7 (MSB)
6
5
4
3
2
0
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1
0 (LSB)
0
x
R
R
Table 20. Load Switch and LDO Control Register
Bit Field
Type
Reset
Description
B7 (MSB) EN_LS_LDO
R/W
0
0 – Disable LS/LDO
1 – Enable LS/LDO
B6
LS_LDO_4
R/W
1
LS/LDO Voltage: 1600 mV
B5
LS_LDO_3
R/W
1
LS/LDO Voltage: 800 mV
B4
LS_LDO_2
R/W
1
LS/LDO Voltage: 400 mV
B3
LS_LDO_1
R/W
1
LS/LDO Voltage: 200 mV
B2
LS_LDO_0
R/W
1
LS/LDO Voltage: 100 mV
B1
0
B0 (LSB) MRRESET_VIN
R/W
0
0 – Reset sent when MR Reset time is met
1 – Reset sent when MR Reset time is met and V_UVLO + V_SLP <
VIN < V_OVP
LS_LDO Bits: Use LS_LDO bits to set the LS/LDO output. The LS/LDO voltage is calculated using the following equation: LS/LDO = 0.8 V
+ LS_LDOCODE x 100 mV. If a value greater than 3.3 V is written, the setting goes to pass-through mode where LS/LDO = VINLS -
V_DROPOUT. The LS_LDO output can only be changed when the EN_LS_LDO and LSCTRL pin has disabled the output.
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