BQ25120A Datasheet, PDF (5/67 Pages) Texas Instruments – Low IQ Highly Integrated Battery Charge Management Solution for Wearables and IoT

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NAME
PIN
NO.
IPRETERM
D1
INT
D2
PG
D4
RESET
MR
SW
SYS
LS/LDO
VINLS
BAT
TS
D3
E1
A4
B5
C5
B4, C4
B1, B2
C3
Pin Functions (continued)
bq25120A
SLUSD08 – MAY 2017
I/O
DESCRIPTION
Termination current programming input. Connect a 0-Ω to 10-kΩ resistor from IPRETERM to
GND to program the termination current between 5% and 20% of the charge current. The
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pre-charge current is the same as the termination current setting. Connect IPRETERM to
GND to set the termination current to the internal default threshold. IPRETERM can also be
updated through I²C.
Status Output. INT is an open-drain output that signals charging status and fault interrupts.
INT pulls low during charging. INT is high impedance when charging is complete, disabled,
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or the charger is in high impedance mode. When a fault occurs, a 128µs pulse is sent out as
an interrupt for the host. INT charge indicator function is enabled/disabled using the EN_INT
bit in the control register. Connect INT to a logic rail using an LED for visual indication of
charge status or through a 100kΩ resistor to communicate with the host processor.
Open-drain Power Good status indication output. PG pulls to GND when V_IN is above V_(BAT)
+ V_SLP and less that V_OVP. PG is high-impedance when the input power is not within
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specified limits. Connect PG to the desired logic voltage rail using a 1kΩ to 100kΩ resistor,
or use with an LED for visual indication. PG can also be configured as a push-button voltage
shifted output (MRS) in the registers, where the output of the PG pin reflects the status of the
MR input, but pulled up to the desired logic voltage rail using a 1kΩ to 100kΩ resistor.
Reset Output. RESET is an open drain active low output that goes low when MR is held low
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for longer than t_RESET, which is configurable by the MRRESET registers. RESET is
deasserted after the t_{RESET_D,} typically 400ms.
Manual Reset Input. MR is a push-button input that must be held low for greater than t_RESET
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to assert the reset output. If MR is pressed for a shorter period, there are two programmable
timer events, t_WAKE1 and t_WAKE2, that trigger an interrupt to the host. The MR input can also
be used to bring the device out of Ship mode.
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Inductor Connection. Connect to the switched side of the external inductor.
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System Voltage Sense Connection. Connect SYS to the system output at the output bulk
capacitors. Bypass SYS locally with at least 4.7 µF of effective ceramic capacitance.
Load Switch or LDO output. Connect 1 µF of effective ceramic capacitance to this pin to
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assure stability. Be sure to account for capacitance bias voltage derating when selecting the
capacitor.
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Input to the Load Switch / LDO output. Connect 1 µF of effective ceramic capacitance from
this pin to GND.
I/O
Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with
at least 1 µF of ceramic capacitance.
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from VIN to
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GND. The NTC is connected from TS to GND. The TS function provides four thresholds for
JEITA compatibility. TS faults are reported by the I²C interface during charge mode.
Copyright © 2017, Texas Instruments Incorporated
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