BQ25120A Datasheet, PDF (38/67 Pages) Texas Instruments – Low IQ Highly Integrated Battery Charge Management Solution for Wearables and IoT

bq25120A
SLUSD08 – MAY 2017
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9.6.3 TS Control and Faults Masks Register
Memory location 0x02h, Reset State: 1xxx 1000 (bq25120A)
Figure 27. TS Control and Faults Masks Register (02)
7 (MSB)
6
5
4
3
2
1
0 (LSB)
1
x
x
x
1
0
0
0
R/W
R
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. TS Control and Faults Masks Register, Memory Location 0010
Bit Field
B7 (MSB) TS_EN
B6
TS_FAULT1
B5
TS_FAULT0
B4
Reserved
B3
EN_INT
B2
WAKE_M
B1
RESET_M
B0 (LSB) TIMER_M
Type
R/W
R
R
Reset
1
x
x
R
x
R/W
1
R/W
0
R/W
0
R/W
0
Description
0 – TS function disabled
1 – TS function enabled
TS Fault mode:
00 – Normal, No TS fault
01 – TS temp < T_COLD or TS temp > T_HOT (Charging suspended)
10 – T_COOL > TS temp > T_COLD (Charging current reduced by
half)
11 – T_WARM < TS temp < T_HOT (Charging voltage reduced by
140 mV)
Reserved
0 – Disable INT function (INT only shows faults and does not
show charge status)
1 – Enable INT function (INT shows faults and charge status)
1 – Mask interrupt from Wake Condition from MR
1 – Mask RESET interrupt from MR . The RESET output is not
masked by this bit.
1 – Mask Timer fault interrupt (safety)
38
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