BQ25120A Datasheet, PDF (27/67 Pages) Texas Instruments – Low IQ Highly Integrated Battery Charge Management Solution for Wearables and IoT

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bq25120A
SLUSD08 – MAY 2017
9.3.17 Thermal Protection
During the charging process, to prevent overheating in the device, the juntion temperature of the die, T_J, is
monitored. When T_J reaches T_(SHUTDOWN) the device stops charging, disables the PMID output, disables the SYS
output, and disables the LS/LDO output. During the time that T_(SHUTDOWN) is exceeded, the safety timer is reset
and the watchdog timer continues to operate if in host mode. The charge cycle resumes when T_J falls below
T_(SHUTDOWN) by T_(HYS).
To avoid reaching thremal shutdown, ensure that the system power dissipation is under the limits of the device.
The power dissipated by the device can be calculated using Equation 5.
P_DISS = P_(BLOCK) + P_(SYS) + P_(LS/LDO) + P_(BAT)
(5)
Where
• P_(BLOCK) = (V_IN – V_(PMID)) x I_IN
• P_(SYS) = I_SYS2 x R_{DS(ON_HS)}
• P_(LS/LDO) = (V_(INLS) – V_(LS/LDO)) x I_(LS/LDO)
• P_(BAT) = (V_(PMID) – V_(BAT)) x I_(BAT)
9.3.18 Typical Application Power Dissipation
The die junction temperature, T_J, can be estimated based on the expected board performance using Equation 6.
T_J = T_A + θ_JA x P_DISS
(6)
The θ_JA is largely driven by the board layout. For more information about traditional and new thermal metrics, see
the IC Package Thermal Metrics application report SPRA953. Under typical conditions, the time spent in this
state is short.
9.3.19 Status Indicators (PG and INT)
The device contains two open-drain outputs that signal its status and are valid only after the device has
completed start-up into a valid state. If the part starts into a fault, interrupts will not be sent. The PG output
signals when a valid input source is connected. PG pulls to GND when V_IN > V_UVLO, V_IN> V_BAT+V_SLP and V_IN <
V_OVP. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic
voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.
The PG pin can be configured as a MR shifted (MRS) output when the PGB_MRS bit is set to 1. PG is high-
impedance when the MR input is not low, and PG pulls to GND when the MR input is below V_{OL(TH_MRS)}. Connect
PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor.
The INT pin is pulled low during charging when the EN_INT bit is set to 1 and interrupts are pulled high. When
EN_INT is set to 0, charging status is not indicated on the INT pin. When charge is complete or disabled, INT is
high impedance. The charge status is valid whether it is the first charge or recharge. When a fault occurs, a 128
µs pulse (interrupt) is sent on INT to notify the host.
9.3.20 Chip Disable (CD)
The device contains a CD input that is used to disable the device and place it into a high impedance mode when
only battery is present. In this case, when CD is low, PMID and SYS remain active, and the battery discharge
FET is turned on. If the LS/LDO output has been enabled prior to pulling CD low, it will stay on. The LSCTRL pin
can also enable/disable the LS/LDO output when the CD pin is pulled low. The CD pin has an internal pull-down.
If V_IN is present and the CD input is pulled low, charge is enabled and all other functions remain active. If V_IN is
present and the CD input is pulled high, charge is disabled.
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